Terence S.-Y. Chen
Latitude Design Systems
Abstract
Silicon photonics has emerged as a disruptive technology for high-bandwidth, low-power communication and computing. However, realizing complex photonic systems requires tight integration of lasers, modulators, detectors, and electronics. In this paper, we review recent developments in advanced 3D packaging that can enable heterogeneous integration of photonic and electronic components. Specifically, we focus on the 3DFabric platform offered by TSMC. We discuss the packaging technologies like chip-on-wafer-on-substrate (CoWoS) and integrated fan-out (InFO) that are part of 3DFabric.
These technologies offer high density integration of chiplets and interposers with through-silicon vias (TSVs) for high-speed signaling. We elaborate on the benefits of 3DFabric for silicon photonics integration. Additionally, we review the initiatives taken by TSMC like the 3DFabric alliance to foster an ecosystem for heterogeneous integration. TSMC is also conducting research into novel bonding approaches to reduce thermal stresses and enable precision alignment during 3D stacking. To aid design of complex photonic systems, electronic-photonic co-design tools like PIC Studio can leverage 3DFabric’s capabilities. While challenges remain, 3DFabric represents a versatile technology platform for advancing integrated silicon photonic systems.
Introduction
Silicon photonics has rapidly established itself as a promising technology for revolutionizing data interconnects and communications. By bringing the techniques of silicon microelectronic fabrication to photonics, silicon photonics enables the integration of lasers, modulators, photodetectors, waveguides, and electronic circuits on a silicon wafer [1]. This monolithic integration can lead to photonic integrated circuits with smaller footprints, higher densities, and lower power consumption compared to using discrete optical and electronic components. Consequently, silicon photonics is poised to meet the growing challenges in chip-scale optical interconnects driven by massive data growth in high performance computing, data centers, and communications.
However, fully realizing the potential of silicon photonics requires heterogeneous integration with other material systems like III-V semiconductors for lasers and Germanium for photodetectors. Combining silicon photonics with other materials can enable diverse active and passive photonic components to be integrated on the same wafer. This is driven by the fact that silicon itself lacks efficient light emission mechanisms and thus external III-V lasers are needed as light sources. But heterogeneous integration comes with several challenges including thermal expansion mismatch, precision alignment, and electrical/optical parasitics [2]. Therefore, advanced packaging techniques that can connect chiplets from different process technologies offer a promising approach to heterogenous integration for silicon photonics.
In this paper, we provide an overview of recent developments in this direction by reviewing the 3DFabric platform offered by TSMC for photonic-electronic integration. As a leading silicon foundry, TSMC is at the forefront of developing and commercializing 3D packaging solutions. 3DFabric provides a diverse set of packaging options that can address the requirements of heterogeneous integration like high density interconnects, fine pitch, and silicon photonics specific co-packaging. We discuss the various technologies like CoWoS and InFO that constitute 3DFabric and elaborate their benefits for photonic systems. Importantly, TSMC is also spearheading research and ecosystem efforts to overcome integration challenges through novel bonding techniques and design ecosystems. With co-design tools like PIC Studio that can harness its capabilities, 3DFabric represents an important technology platform for advancing integrated silicon photonic systems [3].
3DFabric Platform Overview
TSMC formally announced the 3DFabric technology platform in 2019, representing the company’s focus on advanced 3D chip stacking and packaging solutions [4]. 3DFabric builds on TSMC’s expertise in high-volume silicon manufacturing by providing diverse packaging options that complement continued transistor scaling. Using 3DFabric, compute, memory, and analog/RF blocks fabricated in leading CMOS nodes can be integrated in a modular fashion using high density packaging. The platform addresses the growing challenges in heterogeneous integration and chip-level interconnects as dimensional scaling slows down [4].
3DFabric offers a toolkit of packaging technologies and options that can be combined to meet application requirements [5] as shown in figure 1. These broadly include:
lChip-on-Wafer-on-Substrate (CoWoS): This technology enables stacking of high performance logic and memory chips like HBM on a silicon interposer using high density fine pitch interconnects. TSVs provide vertical interconnects enabling I/O counts > 50K.
lIntegrated Fan-Out (InFO): InFO packages chiplets and redistributes connections to larger peripheral pitches thus avoiding TSVs. Versions like InFO-PoP can connect logic and memory dies.
lChip-on-Wafer (CoW): This integrates various dies on a silicon wafer before dicing. Lower cost integration is enabled without individual packaging.
lWafer-on-Wafer (WoW): Similar to CoW but without dicing the integrated wafers. Yields very high-density vertical interconnects.
lSystem-on-Integrated-Chips (SoICs): Combines analog, RF, passives, MEMS, and more with logic dies for system integration.
These packaging options span integration levels from package, wafer, down to chip and offer trade-offs in density, performance, and cost. For silicon photonics, the CoWoS and InFO technologies are highly relevant and offer distinct benefits as discussed in the next section.
Benefits of 3DFabric for Silicon Photonics Integration
TSMC 3DFabric offers several packaging technologies that are well-suited for silicon photonics applications. For instance, the CoWoS (Chip-on-Wafer-on-Substrate) technology provides high-performance, high-bandwidth interconnects that enable the integration of multiple chips in a single package. This technology is ideal for silicon photonics applications that require high-speed data transfer over long distances. Another packaging technology offered by TSMC 3DFabric is InFO (Integrated Fan-Out), which provides high-density interconnects between chips and substrates. This technology is well-suited for silicon photonics applications that require high-density integration of optical devices, circuits, and systems.
TSMC also offers an integrated optical interconnection system (iOIS) for silicon photonics applications in HPC as shown in figure 2 [6]. The iOIS leverages the CoWoS-based composite interposer as the integration platform for HPC and networking applications. The iOIS can meet the diversified technology demands and yield a cost-effective manufacturable solution in alignment with foundry’s 2.5D/3D roadmap.
Heterogeneous integration is critical to fully realize sophisticated photonic systems encompassing lasers, detectors, modulators, electronics, and specialized photonics devices like filters or multiplexers. However, this integration comes with challenges spanning electrical, optical, thermal, and mechanical aspects. There is often a mismatch in process technologies used for silicon photonics components (CMOS) versus III-V lasers (III-V epitaxy) or detectors (Germanium epitaxy). This already creates electrical and optical parasitics that need to be minimized through proximity integration. However, more critically, there is often thermal expansion and lattice constant mismatch which introduces thermomechanical stresses and wafer bowing during high temperature processing steps. Minimizing this requires limiting high temperature excursions typically through direct wafer or die bonding. This also places constraints on alignment accuracy and border tolerances between bonded wafers/chips. The small feature sizes and dense footprints of silicon photonics further exacerbate these requirements. 3DFabric provides pathways to address these heterogenous integration challenges through its advanced CoWoS and InFO packaging options:
High I/O density: Both CoWoS and InFO offer high input/output (I/O) density by enabling TSV and RDL interconnects with small pitches (<40 um). This matches well with the high integration density and number of critical electrical connections in complex photonic integrated circuits.
Thin profile: Integration options like CoWoS allow stacking of multiple thinned dies or wafers (<100 um) thus giving a packaged component with small z-height [8]. This compact integration minimizes electrical parasitics.
Close proximity: CoWoS can bond photonics and electronics chiplets with spacing of 1-10 um thus minimizing optical loss between coupled components. Small form factors are also enabled.
Adaptive integration: Different types of chips and technologies like lasers, modulators, and control electronics can be heterogeneously integrated based on application needs.
Leverage TSVs: The high-density vertical interconnects offered by through-silicon vias (TSV) enables heterogeneous ICs spanning technologies [11].
Silicon substrate: Use of silicon interposers for CoWoS provides better thermal matching and coefficient of thermal expansion compatibility with silicon photonics devices.
By suitable choice of 3DFabric technology (CoWoS vs InFO), number of tiers, interconnect pitches, etc. the specific requirements of a photonic system can be addressed. This provides flexibility in design and assembly not afforded by monolithic integration alone.
(A) in basic configuration, (B) used for Chip-to-Chip optical interconnect, and (C) modularized electrical-optical functionalities of the iOIS platform. Note that all the optical components (OE, Laser, SOA, APD, LNOI, etc.) are optically coupled to CI with estimated coupling loss of ~ 0.015 dB.
3DFabric Initiatives and Ecosystem for Heterogeneous Integration
While the packaging capabilities offered by 3DFabric are compelling, heterogeneous integration of diverse technologies like silicon photonics poses complex co-design challenges. To foster an ecosystem that can leverage 3DFabric for applications like photonic integration, TSMC has pursued some key initiatives:
3DFabric Alliance: This is an industry alliance that brings together partners along the design-manufacturing-packaging value chain for developing heterogenous systems using 3DFabric. It enables design houses, IP vendors, EDA tools, substrate/PCB partners, OSATs, and end-application OEMs to build solutions using TSMC’s 3D/SoIC technologies. The alliance allows partners to gain early access to enable rapid design solutions [7].
InFO Photonic System: TSMC collaborated with partners to develop an integrated photonic system combining lasers, modulators, and control electronics in an InFO package. This demonstrates a heterogeneously integrated silicon photonics platform using 3DFabric, accessible to customers.
Research into bonding: Academia and industry partnerships by TSMC are developing new bonding techniques like surface activated bonding, adhesive bonding, and hybrid bonding. These aim to reduce bonding temperatures and minimize substrate bow and warpage during photonic integration while providing high yield [8].
Design infrastructure: Reference flows, interface standards, multi-die simulations, and integrated tool environments lower barriers to complex heterogeneous design using the 3DFabric platform.
Through these supply chain partnerships, research initiatives, and design ecosystem efforts, TSMC seeks to foster broader adoption of technologies like silicon photonics based on the capabilities of 3DFabric.
Co-Design Tools and Methods for Heterogeneous Photonic Integration
To unleash the integration possibilities enabled by advanced packaging like 3DFabric and accelerate silicon photonics product development, electronic-photonic co-design tools are essential. These tools can provide a unified design flow integrating photonic device design, electronic chip design, system modeling, and package simulation. PIC Studio from LATITUDE is an example of an emerging co-design platform encompassing schematic capture, layout, and system-level simulation for photonic ICs [9] as shown in figure 3 and figure 4. It provides:
Parametric component libraries for photonic devices like waveguides, modulators, lasers etc.
Layout editors tailored for photonic IC design along with DRC/LVS checks.
Spectral, FDTD, and circuit solvers for system-level modeling of photonic circuits.
Artificial intelligence-driven layout synthesis of photonic IC blocks.
Co-simulation interfaces to leading electronic IC design flows.
Such co-design tools can integrate heterogeneous components like driver electronics, modulator arrays, lasers, and detectors for a 3D integrated photonic system design. The packaging constructs available in 3DFabric like interposer designs and interconnect layouts can be incorporated in these tools.
Thermomechanical modeling can validate designs taking into account thermal stresses and deformations induced during fabrication and operation. By leveraging co-design tools like PIC Studio with advanced packaging solutions like 3DFabric, there is tremendous scope to realize complex integrated photonic systems, unlocking new applications.
Conclusion and Outlook
In summary, heterogeneous integration enabled by advanced wafer/chip-scale packaging methods like TSMC’s 3DFabric platform provides a compelling means to meet performance and form factor targets in integrated silicon photonics systems. By tightly combining chiplets containing electronics, photonics, and other technologies, 3DFabric can help overcome fundamental materials and process challenges that hinder monolithic integration alone.
While thermomechanical stresses and electrical/optical parasitics due to process mismatches remain a concern, the high-density interconnects and precision alignment capabilities offered by CoWoS and InFO can mitigate these issues to an extent. Ongoing research into low-temperature and high-accuracy bonding techniques also promise improvements.
Importantly, co-design strategies that can unite system modeling, package-aware floorplanning, and multiphysics simulations can fully exploit 3D integration. Therefore, 3DFabric represents a versatile backend solution for advancing integrated silicon photonic technologies into real-world products and applications.
References
[1] S. Shekhar, et al. “Silicon Photonics - Roadmapping the Next Generation,” 2023.
[2] D. Thomson, et al., “Roadmap on silicon photonics,” Journal of Optics, vol. 18, no. 7, p. 073003, 2016.
[3] J. Yao et al., “Heterogeneous integration for on-chip quantum photonic circuits with single quantum dot devices,” Nanophotonics, vol. 6, no. 3, pp. 577-596, 2017.
[4] “TSMC Announces New 3DFabricTM and System on Integrated Chips (SoIC) Technology Offerings,” TSMC Press Release, Apr. 2019.
[5] “3DFabricTM for HPC,” TSMC Webpage. [Online].
[6] H. Hsia, et al., "Integrated Optical Interconnect Systems (iOIS) for Silicon Photonics Applications in HPC," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 612-616.
[7] “TSMC Launches OIP 3DFabric Alliance to Shape the Future of Semiconductor and System Innovations,” TSMC Press Release, Apr. 2019.
[8] F. JC Lee, et al. “Heterogeneous System-Level Package Integration—Trends and Challenges,” IEEE Symposium on VLSI Technology. IEEE, 2020. p. 1-2.
[9] Latitude Design Automation, “Silicon Photonics Solutions,” 2022. [Online]. Available: https://latitudeda.com/document/41.
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