Technology of Dual Work Function Metal Split-Gate Nanosheet CFETs

Introduction

This article presents the development of dual work function metal (WFM) split-gate nanosheet complementary field-effect transistors (CFETs). This technology integrates advanced epitaxial growth techniques with innovative device fabrication processes, achieving significant performance improvements [1].

Figure 1: 3D schematic of the dual work function metal CFET, illustrating key architectural features of WNxCy and TiN work function metals used for pFET and nFET respectively.

Device Architecture and Fabrication Process

The foundation of this technology lies in its unique epitaxial layer structure and precise manufacturing process. The device employs multiple P/N junctions to achieve electrical isolation between stacked transistors, thereby avoiding complex dielectric isolation techniques. The fabrication begins by thinning the SOI substrate down to 20 nm, followed by the growth of a 108 nm epitaxial Ge buffer layer. This buffer layer undergoes in-situ annealing at 800°C to minimize misfit dislocations at the Ge/Si interface.

Figure 2: Detailed epitaxial growth process flow and transmission electron microscopy image showing the multiple layers of the device structure, including the Ge buffer layer, GeSi channel, and P/N isolation regions.

The fabrication process includes several innovative features, most notably the integration of a ~10 nm thick WNxCy work function metal. By adjusting the N₂/H₂ gas flow ratio during the plasma-enhanced atomic layer deposition (PEALD) process, the properties of these metals can be finely tuned, enabling a tunable 500mV effective work function modulation for the pFET.

Figure 3: Key process flow diagram for the fabrication of dual work function metal split-gate CFETs, highlighting the common gate and split-gate processes.

Material Characteristics and Performance

The outstanding performance of the device stems from its carefully engineered material properties. The Ge₀.₇₅Si₀.₂₅ channel grown on the Ge buffer layer exhibits fully tensile strain with a strain value reaching 1.12%. This strain engineering enhances carrier mobility and overall device performance.

Figure 4: Range of effective work function modulation of WNxCy (500 meV) and comparison of its conductivity characteristics with industry standards.

The dual work function metal configuration enables independent gate control of n-type and p-type field-effect transistors, which is critical for advanced logic design. The device achieves an excellent threshold voltage matching ratio (|VTP|/|VTN|) of 0.93, the best reported among monolithic nanosheet CFETs.

Figure 5: Current-voltage characteristics and voltage transfer curves demonstrating the electrical performance of the dual work function metal split-gate CFET.

Performance Achievements and Technological Impact

The implementation of dual work function metals has led to several technological breakthroughs. The device demonstrates a record gain of 61 V/V among monolithic nanosheet CFETs. At VDD = 0.75 V, the hold state noise margin (HSNM) reaches 0.24 V, marking a significant improvement over single work function metal design.

Figure 6: TEM image and EDS elemental mapping showing the cross-sectional view of the Ge₀.₇₅Si₀.₂₅ split-gate CFET, clearly depicting the wrap-around dual work function metal structure.

This technology paves the way for advanced process nodes beyond traditional nanosheet architectures. It enables matched threshold voltages while maintaining independent gate control, offering greater design flexibility for complex logic circuits.

The successful application of dual work function metals in split-gate CFETs demonstrates a major advancement in semiconductor technology. The matched threshold voltages, enhanced noise margins, and record-setting gain clearly reflect the practical value of this architecture in future semiconductor devices.

Reference

[1] B.-W. Huang et al., "WNxCy VT Tuning of Split Gate Nanosheet CFETs with Dual Work Function Metals Achieving 0.93 VT Match/ Improved 0.24V Noise Margin/ Record Gain of 61V/V," in 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024.