Introduction
In recent years, silicon photonics has made significant advancements to enable high-performance optical links that can compete with traditional material systems like indium phosphide, gallium arsenide, and lithium niobate. This has been achieved by leveraging novel integration techniques within the silicon photonics manufacturing flow, enabling simultaneous low-cost and high-performance alongside the benefits of silicon's economies of scale.
In this article, we will explore a demonstration of an optical link operating at 53.125 Gbps PAM4 and 53.125 Gbps NRZ, showcasing three types of advanced integration: (1) co-integration of optical device drivers with a TX & RX PHY in a DSP chip, (2) heterogeneous integration of III-V devices onto a silicon photonics platform, and (3) monolithic integration of 45nm CMOS transistors with silicon photonics passive and active devices.
Silicon Device Integration
The digital signal processor (DSP) chip is fabricated in an advanced FinFET process with the electroabsorption modulator driver monolithically integrated and co-designed with the TX PHY output.
The transmit OpenLight SiPho 4-channel coarse wavelength division multiplexing (CWDM) Photonic Integrated Circuit (PIC) is fabricated in the Tower Semiconductor PH18DA process. The fabrication flow, illustrated in Fig. 1(b), involves patterning the SOI wafer with photonic devices, bonding a III-V die to the top surface of the wafer, removing the III-V die substrate, further processing and patterning the III-V device area, and finally forming the back end of line metal interconnects. Through this process, a single silicon photonics wafer can support multiple types of III-V device functionality, such as a III-V gain region for tunable lasers and a separate III-V electroabsorption regime for heterogeneous silicon/III-V electroabsorption modulators. The TX PIC was flip-chipped onto a metal-organic substrate, and a low-loss edge coupling pigtailing process was used to couple light from the PIC to SMF fiber, as shown in Fig. 2(a).
The 16-channel receive chip is fabricated in the GlobalFoundries Fotonix™ process, which monolithically integrates 45nm CMOS devices and photonics on the same SOI wafer, as illustrated in Fig. 1(a). The receive chip incorporates a high-speed transimpedance amplifier, including cascaded stages of a shunt-inverter TIA section, inverter-based Cherry-Hooper amplifier, variable gain amplifier, continuous time linear equalizers, pre-driver, and output pad-driver. On-chip bias current generation and monitoring functionality is also implemented, and the entire chip utilizes a digital SPI controller for register read and write operations. A V-groove spot-size converter brings light from standard 10μm MFD single-mode fiber to on-chip waveguides, while on-chip polarization splitters & rotators enable polarization diversity into the high-speed photodetectors.
Optical Link Experiment
The block diagram schematic of the experimental setup is shown in Fig. 3. The TX EVK was connected to the DSP EVK with 12-inch RF cables, with an additional total of 4 inches of PCB transmission lines on the respective EVK boards.
To measure eye diagrams, the receive PIC TIA output is connected to a Keysight digital communication analyzer (DCA) with 14 inches of coaxial RF cables, as shown in Fig. 3(a). For bit error rate testing, the TIA output is directed through 20 inches of coaxial cables to the 53G DSP. DC blocks are used between the TIA output and both the DCA and the 53G DSP chip since the TIA has a common mode voltage output of 0.9 V.
The DSP chip contains a feed-forward equalizer (FFE) in the PHY TX, which is used to compensate for any bandwidth limitations in the transmit PIC. The DSP PHY RX utilizes an adaptive equalizer. SMF fiber is used to directly connect the transmit PIC modulated output to the receive PIC.
Measured eye diagrams at 53.125 Gbd NRZ and 26.5625 Gbd PAM4 are shown in Fig. 4. The NRZ eye in Fig. 4(a) and PAM4 eye in Fig. 4(b) are without any additional DSP processing on the DCA. The eye shown in Fig. 4(c) is with offline processing in the DCA to implement a 5-tap TDECQ feed-forward equalizer filter. The reported 1.91 dB TDECQ value of the TIA electrical eye is measured through the entire DSP to transmit PIC to receive PIC chain, demonstrating the overall link quality.
The DSP chip contains an integrated bit error rate monitor. At 26.5625 Gbd PAM4 and 150 μA average photodetector current measured through the photodetector bias pin, a stable 1e-6 BER is measured before any forward error correction. At a 170 μA average photocurrent, the 56.125 Gbd NRZ signal is received error-free (BER<1E-12) without any forward error correction.
Conclusion
In this tutorial, we have demonstrated an optical link at 53.125 Gbps PAM4 and 53.125 Gbps NRZ, where the DSP chip incorporates a co-designed PHY and EAM driver, the transmit photonic chip heterogeneously integrates III-V devices to form tunable lasers and electroabsorption modulators, and the receive photonic chip monolithically integrates CMOS electronics and photonics. This demonstration of an optical link with leading-edge silicon photonics process nodes paves the way for future silicon photonic chips to leverage the same process integrations for next-generation systems.
Reference
[1] K. Szczerba et al., "53 Gbps Optical Link with Co-designed DSP and Integrated EAM Driver, Heterogeneously-Integrated Transmitter, and Monolithically-Integrated Receiver," 2024.
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