Introduction
Silicon photonics is an emerging technology that builds photonic integrated circuits (PICs) directly on the mature silicon manufacturing platform used for modern electronics. By leveraging existing semiconductor infrastructure and know-how, silicon photonics enables highly advanced PICs with unprecedented yield, density, and cost advantages compared to traditional photonics manufacturing. This tutorial will cover the current state-of-the-art, key building blocks, manufacturing processes, design considerations, and future technology trends for silicon photonics based on the 2024 Integrated Photonic Systems Roadmap (IPSR-I) published by leading industry groups.
Silicon Photonics Overview
The core of silicon photonics PICs uses a silicon-on-insulator (SOI) wafer, where a thin silicon layer acts as the waveguide core surrounded by a buried oxide insulation layer. This high index contrast waveguide platform enables highly compact photonic devices and dense integration similar to modern electronics. Silicon photonics currently operates in the near-infrared wavelength range of 1-4 μm, covering the crucial telecommunications bands at 1300 nm and 1550 nm.
The ability to fabricate PICs in conventional CMOS foundries provides remarkable scalability and manufacturability advantages. As of 2024, there are approximately 4-8 CMOS foundries, 4 integrated device manufacturers (IDMs), and 20 research institutes worldwide offering mature silicon photonics processes on 200mm or 300mm wafers. These advanced manufacturing capabilities have enabled silicon photonics to become the technology of choice for leading datacenter and telecommunications firms, collectively deploying tens of millions of transceivers.
Key Building Blocks
Silicon photonics leverages high index contrast to enable a wide variety of compact passive and active photonic devices that can be densely integrated on a single chip. Some key building blocks include:
Waveguides: Silicon waveguides with cross-sections around 500 nm x 220 nm confine light tightly for highly compact routing and low-loss propagation below 1 dB/cm expected by 2030.
Filters: Wavelength-selective filters like arrayed waveguide gratings (AWGs) can multiplex over 100 channels onto a single waveguide with anticipated crosstalk better than 40 dB by 2030.
Photodetectors: Epitaxially grown germanium photodetectors monolithically integrated on the waveguides provide high responsivity up to 1.1 A/W while scaling to 300 GHz bandwidths by 2035.
Modulators: Silicon modulators utilize the plasma dispersion effect to achieve high-speed phase modulation up to 800 Gbaud by 2035 using compact Mach-Zehnder interferometers or resonant ring modulators.
Fiber Couplers: Grating couplers enable vertical fiber coupling with wideband <0.2 dB insertion loss by 2035, while edge couplers can provide <0.5 dB loss from 500-800 nm bandwidth in the same timeframe.
Other key components outlined in the roadmap include isolators, laser/gain integration through heterogeneous processes, optical switches, and electronic-photonic integration discussed later.
Manufacturing Processes
To produce silicon photonics PICs, a complete CMOS process flow is leveraged with several photonic-specific modules added, as illustrated in the process cross-section in Figure 1. Some key process elements include:
Waveguide Patterning: SOI waveguides are patterned using 193nm deep UV immersion lithography and dry etching with sidewall roughness control <1 nm anticipated by 2030.
Germanium Epitaxy: Epitaxially grown Ge enables waveguide-integrated photodetectors, utilizing selective area growth in a damascene process flow.
Doping: Implants are used to form p-n junctions for modulators and detectors, with activation at <700°C to enable back-end electronic integration.
Table 1: Technology needs for various other technology modules
Thermal budget | [unit] | 2024 | 2030 | 2040 |
a-Si to poly-Si | [C] | 600 | 600 | 600 |
Dopant implant activation | [C] | 900 | 800 | 700 |
Planarization | [unit] | 2024 | 2030 | 2040 |
Required flatness | nm | 20 | 10 | 5 |
Uniformity | % | 2 | 1 | 0.5 |
Selectivity | dilution/pH/slurry | interdependent | interdependent | interdependent |
Dicing/cleaving | [unit] | 2024 | 2030 | 2040 |
Position accuracy | [μm] | 50 | 20 | 10 |
Metal deposition | [unit] | 2024 | 2030 | 2040 |
Thermal budget | [C] | 450 | 400 | 350 |
Wafer bonding | [unit] | 2024 | 2030 | 2040 |
Thermal budget | [C] | 300 | 250 | 200 |
Cladding Deposition: Silicon oxide, nitride, and other dielectrics are deposited and planarized using processes like chemical vapor deposition and chemical mechanical polishing (CMP).
Metallization: Metal depositions are used to form ohmic contacts, heaters, and eventually interconnect wiring as for standard electronics.
Heterogeneous Integration: Techniques like wafer bonding, die/die-to-wafer hybrid integration, and micro-transfer printing enable integration of III-V and other compound semiconductor active devices like lasers.
This mature process flow enables silicon photonic circuits to be fabricated with essentially the same infrastructure as advanced CMOS logic nodes, providing unparalleled manufacturing capabilities.
Design Automation
A crucial component of the silicon photonics ecosystem is the process design kit (PDK), which models component behavior, specifies design rules, and provides a library of pre-validated building blocks. PDK maturity for high-volume fabs and IDMs is increasingly reaching parity with electronic PDKs, incorporating compact models, layout vs schematic/circuit verification, and bidirectional electronic-photonic design automation.
However, for lower volume research fabs, PDK maturity remains a critical gap and area for development. Robust compact models and capturing process variability through statistical/corner case models will be essential for first-time-right designs, especially as integration complexity grows.
Table 2: PURPLE BRICK WALL: SUPPLY CHAIN LEVEL
Today's situation including expected evolutions in coming years | Substantial challenges (technical Desired long-term situation or economic) that form barriers for further evolution | Desired long-term situation |
Year | Transition to advanced litho nodes | Process Design Kits (PDK) and Photonic Design Automation (PDA) | Processed wafer price | Heterogeneous Integration |
2024 | Only limited number of manufacturing platforms on 200/300mm with 193nm immersion lithography | ㆍMaturity of PDKs owned by pure-play fabs modest in comparison to EIC PDKs ㆍMaturity of proprietary PDKs owned by fabless end-users and IDMs closer to maturity of EIC PDKs | High processed wafer price as compared to EICs (in a similar technology node) despite lower number of masks for photonic SOI technologies | Only (limited) cases of integration compliant process flows for heterogeneous integration in industrial manufacturing environments |
>2030 | Volumes not large enough to justify the higher technology development cost for fabs currently operating with 193nm dry lithography | ㆍPDKs owned by R&D fabs and low-volume fabs lack sophisticated compact models ㆍLack of process variablity information in PDKs owned by R&D and low-volume fabs ㆍFurther development necessary for robust models for compelx passive devices. | Low volume, NRE costs associated with custom process development | ㆍNRE Costs ㆍCompliance with existing process flows ㆍCompliance with CMOS processes ㆍLack of standardization ㆍBringing heterogeneous integration to high volume production in a CMOS fab |
>2035 | Larger number of manufacturing platforms on 200/300mm with 193nm immersion lithography | ㆍCompact models in PDKs owned by R&D and low-volume fabs ㆍUnified design flow for EIC and PIC for current and emerging application usecases ㆍStandardized design flows for current and emerging application usecases ㆍFirst-time right design ㆍLVS and full end-to-end simulation are an absolute necessity | Volumes large enough to make the costs associated with NRE and mask costs become an acceptable fraction of the product cost. | ㆍSupply chain established to accommodate a wide variety of heterogenous material and device combinations ㆍStandard wafers/materials/chiplets for heterogeneous integration ㆍLeveraging electronics-type heterogenous integration |
Year | Prototyping cycle | Inline control & test | Second sourcing/Foundry portability | Assembly |
2024 | Slow cycle times leading to slow innovation | ㆍDesign for Test ㆍWafer level inspection ㆍProcess control and monitoring | Critical reliance on single supplier for PIC development | Fragmented landscape of solutions fabless companies with a few Si photonics products |
>2030 | ㆍManufacturing of PICs typically has a long design , fabrication, test cycle and requires too many iterations ㆍMultiplicity of causes ㆍFaster innovation of photonics can be obtained by eflicient MPW and good use of DOEs | ㆍModels with associated parameter extraction procedures ㆍVariability should be part of models after extraction on silicon | ㆍHigh risks for end-users ㆍHigh barriers to entry for new chip manufacturers ㆍLarge variety of fab process capabilities ㆍLittle portability through design library and models ㆍMoreover process are not standard/aligned making PDK alignement extremely dificult ㆍEDA tools less evolved than for CMOS making porting even more difficult | ㆍStandardized photonic-electronic-fiber co-assembly with large bandwidth, low cost, high throughput, and high tolerance ㆍRobotized and standardized pick-and-place methodologies ㆍStandardized solutions for co-assebly with microfluidics |
>2035 | ㆍApplication-specific PDKs ㆍProgrammable photonics (as a means to build and test prototypes much more rapidly) | More second sourcing and foundry portability options | Well-developed supply-chains for standardized assembly |
More broadly, the ability to seamlessly co-design photonics with electronics in a unified environment will be critical for future systems benefiting from tight electronic-photonic integration. Investments are ongoing in sophisticated EDA tools supporting this convergence.
Quality, Reliability and Environmental Impact
Thanks to the maturity of the silicon platform, studies have demonstrated excellent reliability for passive silicon photonic devices under high optical power, as well as reliable operation of active germanium components under thermal and electrical stress.
Integrating direct epitaxial growth of III-V materials introduces some environmental and safety challenges that will require mitigation for high-volume CMOS manufacturing. Strategies like dedicated III-V modules and tool chambers can help in the interim before processes are fully adapted.
Overall, leveraging existing CMOS infrastructure helps minimize the environmental impact for silicon photonics compared to developing entirely new manufacturing facilities. With appropriate controls, these impacts can be managed concurrently with electronic chip manufacturing.
Emerging Applications
While today's commercial driver for silicon photonics remains transceivers and interconnects for datacom/telecom, the low cost and miniaturization enabled by this platform is opening a vast range of other potential applications:
High Performance Computing: Utilizing integrated photonics for chip-to-chip and rack interconnects can provide the bandwidth density and energy efficiency required for emerging AI/ML workloads.
Sensing: Low-cost, high-volume silicon photonic sensors can be ubiquitously deployed for applications like LIDAR, structural monitoring, medical diagnostics, and more.
Quantum Computing: With continued research, silicon photonics provides a promising path towards compact, scalable quantum optical circuits and components.
Future Technology Trends
Looking ahead, some key trends and challenges highlighted in the IPSR-I include:
Sustained Lithography Scaling: Maintaining the historical lithography scaling roadmap of achievable feature sizes will be essential, potentially requiring a transition to higher NA extreme ultraviolet (EUV) lithography.
Light Source Integration: Merging laser sources and related gain materials will be a major driver, necessitating reliable heterogeneous integration processes across the supply chain.
Materials Integration: Beyond lasers, incorporating materials like lithium niobate, graphene, ferroelectrics and 2D compounds can potentially boost performance and new functionalities of the platform.
System-Level Design: As photonics is pervasively deployed, new design flows and methodologies centered around full system-level optimization of performance, power, bandwidth, cost and reliability will emerge.
Integrated Electronic-Photonic Systems: Ultimately, the tightest possible monolithic electronic-photonic convergence provides the most optimal energy efficiency, interconnect density, and latency that will be required for future computing system architectures.
Conclusion
Silicon photonics is a revolutionary technology poised to transform a diverse array of industries by providing a scalable, high-yielding platform for manufacturing highly advanced photonic integrated circuits. By marrying light waves with the ubiquitous semiconductor manufacturing used for modern electronics, silicon photonics technology overcomes many traditional barriers in cost, performance, and scalability that have historically limited photonics adoption. As highlighted in industry roadmaps, key innovations in lithography, materials integration, design automation, and system-level design will continue enabling exponential growth in this disruptive technology, tremendously impacting fields as varied as telecommunications, computing, sensing, quantum information processing, and beyond.
Reference
[2] Integrated Photonic Systems Roadmap - International (IPSR-I), "2024 IPSR-I Silicon Photonics Updated V2," March 2024.
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