Silicon Photonic WDM Receiver with Ring Resonator Filters

Introduction

With the rise of artificial intelligence and machine learning services, the demand for high bandwidth in data center interconnects is continuously growing. Wavelength division multiplexing (WDM) is a promising technique to meet this demand, allowing multiple optical signals at different wavelengths to be transmitted over a single optical fiber. Silicon photonics, which leverages standard CMOS fabrication processes, offers a cost-effective solution for implementing WDM systems, making it particularly attractive for co-packaged optics (CPO) and photonic chiplets.

A key component in WDM systems is the wavelength filter, responsible for separating the different wavelength channels. Ring resonator filters (RRFs) are ideal for this purpose due to their small size, high integration density, and excellent wavelength selectivity. However, as the number of WDM channels increases, careful design and implementation of RRFs become crucial.

One of the main challenges with RRFs is their sensitivity to temperature and fabrication process variations, which can significantly impact their performance. Therefore, precise and efficient temperature control of RRFs is essential for stable WDM operation.

In this tutorial, we present a hybrid-integrated silicon photonic WDM receiver capable of processing 4 wavelength channels, each operating at 28 Gb/s NRZ data rate, utilizing thermally controlled RRFs.

System Implementation

The WDM receiver consists of a photonic integrated circuit (PIC) and an electronic integrated circuit (EIC), as shown in Figure 1(a). The PIC contains four RRFs with a 12-μm radius, sharing a bus waveguide. Each RRF has a Germanium photodetector (Ge-PD) connected to its drop port. The EIC comprises four transimpedance amplifiers (TIAs), one for each WDM channel.

Figure 1: (a) Block diagram of the Si photonic WDM receiver and its temperature controller. (b) Photograph of the Si photonic WDM receiver.

The system includes a temperature controller (TC) composed of an FPGA, four analog-to-digital converters (ADCs), and four drivers (DRVs). The TC monitors the average power received by each Ge-PD through the corresponding RRF and adjusts the RRF's on-chip heater voltage (VH) to maintain the desired wavelength.

Figure 1(b) shows a photograph of the fabricated Si photonic WDM receiver, with the PIC fabricated using IHP's 0.25-μm Si photonic process and the EIC fabricated with a 28-nm CMOS process.

Single Channel Implementation

Figure 2(a) illustrates the block diagram for a single WDM channel. The RRF has a 12-μm radius, a free spectral range (FSR) of 8.3 nm, and a Q-factor of 2200. The Ge-PD is connected to the RRF's drop port, and the measured receiver opto-electronic (O/E) 3-dB bandwidth is 22 GHz.

Figure 2: (a) Block diagram of a single WDM channel in the WDM receiver. (b) Simulated 28-Gb/s eye diagram and O/E frequency response of a single WDM channel.

The TIA and the 50-Ω driver in the EIC are based on CMOS inverters, with inductive peaking employed to enhance the receiver bandwidth without increasing power consumption. Figure 2(b) shows the simulated 28-Gb/s eye diagram and the frequency response of a single WDM channel.

The TIA includes a DC offset cancellation (DCOC) loop consisting of a low-pass filter, an operational amplifier (OP-AMP), and a FET for current sinking. To monitor the average optical power transmitted through the RRF, a received signal strength indicator (RSSI) is implemented using the OP-AMP output signal in the DCOC loop. This circuit copies the DC current level from the PD to the TIA and converts it to a monitoring voltage (VM), which the TC uses to determine and maintain the required RRF on-chip heater voltage (VH) against external temperature fluctuations using the dithering method.

Measurement Results

Figure 3(a) presents the measured bit error rate (BER) curve with an eye diagram for 28-Gb/s, PRBS-31 input data. With a -6-dBm input optical power to the Ge-PD, a BER of 10^-12 is achieved. The power consumption for one TIA is 27 mW.

Figure 3: Measurement results of (a) BER curve with eye diagram for 28-Gb/s, PRBS-31 input data, and (b) thermal stress test.

Figure 3(b) shows the measurement result for the thermal stress test. Each curve represents the VH applied to each RRF when the receiver undergoes a temperature change from 30°C to 20°C and back to 30°C with a rate of 0.05°C/s while receiving 28-Gb/s data. The accumulated eye diagrams for the four WDM channels are also shown. As can be observed, the TC correctly produces the VH signal for each channel, maintaining good eye quality despite the temperature variations.

Conclusion

This tutorial article presents a hybrid-integrated silicon photonic WDM receiver capable of processing 4 wavelength channels at 28 Gb/s per channel, leveraging thermally controlled ring resonator filters. The system demonstrates stable operation under temperature variations, thanks to the efficient temperature control implemented by the FPGA-based temperature controller. This work highlights the potential of silicon photonics for high-bandwidth WDM applications in data center interconnects, co-packaged optics, and photonic chiplets.

Reference

[1] J.-H. Lee, H.-K. Kim, M. Kim, Y. Jo, S. Lischke, C. Mai, L. Zimmermann, and W.-Y. Choi, "A 112-Gb/s Hybrid-Integrated Si Photonic WDM Receiver with Ring-Resonator Filters," in Proceedings of the IEEE International Conference on Photonics, Seoul, South Korea, 2024, pp. 1-2. doi: 979-8-3503-9404-7/24/$31.00.