Packaging and Test Technologies for Integrated Photonics

Introduction

The rapid growth of integrated photonics (PIC) has led to numerous innovative solutions for various applications. However, a bottleneck exists in the form of assembly and packaging, hindering the commercialization of full system solutions. This chapter explores the challenges and advancements in PIC packaging and test technologies.

Figure 1. Overview of PIC packaging technologies [1].

Challenges of Current Packaging Techniques:

• Serial processes: Traditional packaging involves a package-by-package approach, where interconnects are completed after placing the photonic device in the housing. This serial process is slow, labor-intensive, and limits scalability.

• Limited throughput: Due to the serial nature, package-level testing also suffers from low throughput, impacting production efficiency.

• Inflexibility: The current methods lack flexibility in design and process flow, making it difficult to adapt to diverse applications and emerging demands.

PIC Packaging Technologies

PIC packaging is a complex task requiring expertise in various areas, including:

• Advanced packaging materials

• Photonic and electronic device integration

• Precision optical assembly

• High-speed electrical design

• Thermal management

• Reliable mechanical design

• Understanding end-user applications

Effective PIC packaging and test technologies should consider all these aspects, ensuring efficient, high-throughput, and cost-effective solutions.

Transceiver Package Design

A typical example of a PIC package is the optical transceiver module. This compact package integrates various components:

• Active and passive photonic components

• Electrical ICs (amplifiers, drivers)

• Printed circuit boards (PCBs) for both photonic and electronic devices

• Mechanical structures for alignment, heat dissipation, and shielding
  

The primary challenge lies in combining these diverse functionalities within a compact, low-cost module. Key challenges include:

• Efficient coupling between optical fibers and photonic chips

• Integration of laser sources and electronic ICs

• High-speed electrical signal routing

Figure 2. PIC packaging technology should consider all aspects of packaging and test, including; design standards; optical-electrical packaging processes; device integration; thermal management and reliability.

Figure 3. Schematics showing the configuration and main components in a standard pluggable optical transceiver module.

Optical Packaging

Current state-of-the-art techniques involve permanent bonding of optical fibers to the photonic chip using UV-curable or heat-curable epoxy. This process is:

• Labor-intensive

• Requires high precision alignment

• Needs long-term mechanical and thermal stability

Two main coupling schemes exist:

• Edge coupling: Offers broad spectral operation and allows for mode size converters. However, it's slow and can only be used for 1D linear arrays, limiting the number of outputs per device facet.

• Grating coupling: Easier to manufacture and can be designed for any mode size. However, it has limitations in spectral bandwidth, suffers from polarization sensitivities, and requires expensive special fibers.

Innovative approaches like using integrated v-grooves for passive alignment are emerging to address challenges with edge coupling.

Figure 4. Schematics showing the evolution from pluggable optical transceivers to co-packaged systems. The drive is to move the transceiver closer to the switch component using electrical interposers [1].

Figure 5. Photonic devices often have different mode sizes, ranging from 1 to 10 μm. The left image shows the alignment tolerance for 1-dB loss for various mode sizes. The right image shows UV curing of optical fibers in a photonic package. Source: Images: Tyndall & ficonTEC.

Figure 6. Fiber coupling to silicon photonic waveguides can be achieved using a surface grating or edge couplers. Edge coupling is becoming more common as it offers board spectral operation and mode size converters can be fabricated on the photonic devices to match the MFD of the coupling fibers.

Figure 7. Using a microlens on the photonic device to couple to a ribbon FA (left image) and attachment of a microlens to a silicon photonic device in a packaging machine [1].

Figure 8. ZEMAX simulations of edge coupler expanded beam paradigm. (A) Coupling efficiency as a function of distance. Tolerance of displacement (B) and angle (C) as a function of the expanded beam diameter [1].

Electrical Packaging

Electrical packaging is often overlooked but can significantly impact production costs, especially in high-speed transceivers. Key aspects include:

• High-speed electrical connectors: V, K, or GPPO RF connectors are used.

• Co-packaging: Integrating electronic chips closer to the PIC using electrical interposers, becoming increasingly important for higher frequencies.

Wire bonding is the most common method for electrical connections within a package, with different types used for various applications:

• Gold or aluminum ball/wedge bonding: Used for DC applications.

• Ribbon wire bonds: Used for high-speed (RF) signals.

Electrical interposers are used when there's a mechanical mismatch between the photonic device and PCB. These interposers can be made from ceramics, silicon, or glass.

For even higher frequencies (>20 GHz), flip-chip packaging with complex electrical interposers is necessary. These interposers include:

• Through-substrate vias (TSVs)

• Multilevel electrical redistribution layers (RDLs)

Careful design and material selection are crucial for these interposers to minimize signal losses, heat transfer, and mechanical stress.

Figure 9. Examples of electrical wire bonds used in photonic packages. Gold ball bond (left image) and Ribbon bond (right image) [1].

Figure 10. AlN ceramic interposer is used to fan-out RF transmission lines from the photonic device to the larger pitched PCB (left image). The larger pitch PCB transmits the RF lines to the high-speed connectors (right image) [1].

Figure 11. Co-packaging of photonic device and electronic ICs on a silicon electrical interposer (left image). X-ray image of the same package showing the solder bumps and through silicon vias connection to the underside of the interposer. This enables the assembly to be directly placed and soldered onto a PCB motherboard (right image) [1].

Figure 12. (Left) 2.5D packaging of a PIC with multiple TIAs on a silicon interposer with TSVs. (Right) The complete photonic package. A high-speed PCB fans out electrical connections to RF and DC connectors at the edges of the board. One side of the package is reserved for optical interfacing.

Hybrid Laser-to-PIC Packaging

Since PICs, like silicon and silicon nitride (SiN) devices, lack an intrinsic light source, various approaches are used to integrate them:

• Off-package light source: This conventional approach uses fiber coupling, resulting in a larger module footprint but allowing independent thermal management of the light source and PIC.

• In-package light source assembly (hybrid integration): This method uses micro-optics for coupling and offers a compact design while minimizing thermal crosstalk. However, it's technically challenging and requires fast assembly processes.

• Direct bonding (heterogeneous integration): This approach involves techniques like transfer printing to directly bond the light source on the PIC chip. While achieving fast integration and potentially lower costs, it lacks pre-bonding device testing and can introduce thermal challenges.

Figure 13. (A) Manufacturing chain of photonic integrated circuit with (B) distribution of test processes from a design to product [2].

Figure 14. Reproducibility of automated optical alignment systems [3].

Packaging Design Rules and Standardization

Standardizing design rules for photonic packaging is gaining traction, offering several benefits:

• Reduced design burden: Predefined rules lessen the design workload for researchers and engineers.

• Streamlined design-to-device process: Established rules facilitate a smoother transition from design to actual devices.

Industry collaboration is leading to the development of:

• Packaging/assembly design kits (ADKs): Provide pre-designed components and layouts for faster and more reliable packaging.

• Packaging design rules (PDRs): Specify guidelines for aspects like:

  • Pitch of grating arrays on PICs

  • Pitch of fibers in fiber arrays

  • Pitch and metallization type of electrical bond pads

  • Location of coupling elements relative to electrical interconnects

Implementing these rules, especially during the layout phase, can prevent costly design errors and ensure compatibility with existing packaging solutions. ADKs are being integrated into software tools, allowing designers to easily access and implement these rules alongside their photonic designs.

Figure 15. An example of the modular test framework with open standard data formats [2].

Future Advancements

Future developments in PIC packaging and test technologies will likely focus on:

• Integrated design tools: Seamless integration of various software tools used for optical, electrical, thermal, and mechanical design phases, enabling designers to visualize the impact of changes across different aspects of the package.

• Cost modeling software: Development of software tools that link with design tools, allowing designers to assess the cost implications of various design decisions and optimize packaging for both performance and cost.

Conclusion

Packaging and testing are crucial aspects of PIC technology, directly impacting production costs, scalability, and overall system performance. While challenges exist, ongoing research and development efforts are paving the way for more automated, efficient, and cost-effective packaging and test solutions, ultimately accelerating the widespread adoption of PICs in various applications.

Reference

[1] M. Glick, L. Liao, and K. Schmidtke, Integrated Photonics for Data Communication Applications. Elsevier, 2023.

[2] S. Latkowski, W. Yao, D. Pustakhod, X.J.M. Leijtens, K.A. Williams, Test methods and processes in manufacturing chain of photonic integrated circuits, in: 2018 20th International Conference on Transparent Optical Networks (ICTON), July 2018, pp. 1-4. https://doi.org/10.1109/ICTON.2018.8473652.

[3] S. Latkowski, D. Pustakhod, M. Chatzimichailidis, W. Yao, X.J.M. Leijtens, Open standards for automation of testing of photonic integrated circuits, IEEE J. Sel. Top. Quantum Electron.