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On-Chip System Cuts Power Consumption, Drives Data Center Efficiency


atomic layer deposition systems
Ph.D. student Jessica Peterson and professor John Conley discussing the operation of one of his group’s atomic layer deposition systems. Courtesy of Oregon State University.

CORVALLIS, Ore., May 25, 2023 — According to the U.S. Department of Energy (DOE), a data center can consume up to 50× more energy per square foot of floor space than a typical office building. Data centers account for roughly 2% of all electricity use in the U.S., according to the DOE.

As a result, interconnects characterized by high energy-efficiency systems are needed to reduce power consumption.

In response, researchers at Oregon State University (OSU) and Baylor University have developed a silicon photonics method that reduces the amount of energy consumed by photonic chips used in data centers and supercomputers. Specifically, the energy-efficient method compensates for temperature variations that degrade the chips.

The researchers targeted silicon micro-ring resonators (Si-MRRs) in the work; according to the researchers, Si-MRRs play essential roles in on-chip wavelength division multiplexing (WDM) systems. This is due to their ultracompact size and low energy consumption. However, the resonant wavelength of Si-MRRs is very sensitive to temperature fluctuations and fabrication process variation. “Typically, each Si-MRR in the WDM system requires precise wavelength control by free carrier injection using PIN diodes or thermal heaters that consume high power,” the researchers said.

As a result, significant energy has been required to keep the performance of these chips high and their temperature stable.

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