Introduction
As the semiconductor industry transitions from monolithic system-on-chip (SoC) designs to heterogeneous integration with multiple chiplets in a package, mastering the design and implementation of interconnects has become critical. What was once a relatively straightforward process of laying down copper traces has evolved into an intricate choreography of tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even optical interconnects. In this tutorial, we'll explore the key considerations and best practices for developing robust interconnect solutions to unlock the full potential of chiplets and advanced packaging.
The Imperative for More Interconnects
As Chris Mueth, Senior Manager at Keysight, explains, "As data rates increase and we push the limits of what data can be pushed down a physical channel, parallel processing or nested parallel processing will be required to gain speed. The implication here is more interconnects are required than ever before."
This proliferation of interconnects is particularly evident with chiplet designs, where data must seamlessly flow in and out of each chiplet to connect it to other components in the package. While potentially more complex, the chiplet approach offers a significant advantage in power savings.
"Regular chips have big power-hungry drivers on their output pins to drive signals through long PCB traces," said Marc Swinnen, Director at Ansys. "But chiplets don't need those power-hungry drivers because 2.5D interconnects are much shorter, allowing the use of smaller, lower-power I/O drivers on each chiplet."
Overcoming Physical Limits
The underlying physics of packing more transistors into a fixed area is a key driver behind interconnect complexity. As Frank Schirrmeister, VP at Arteris, notes, "You rip apart what used to be on a chip into multiple chiplets. The way you communicate on-chip needs to be extended to inter-chiplet communication, but the complexity has grown tremendously."
While digital logic continues scaling into angstrom dimensions, shrinking wire widths increases resistance and capacitance while introducing new physical effects like excess heat, signal slowdown, and signal integrity issues. Overcoming these obstacles requires new materials with higher electron mobility, wider data pathways, and comprehensive workload modeling to optimize 3D interconnect layout across the X, Y, and Z axes.
"You're only as fast as the slowest interconnect in your design," said Mick Posner, VP at Synopsys. "Everything has to scale at the same time - local interconnects, global interconnects, and vertical connections through TSVs."
Interconnect Taxonomy
In advanced packages, a hierarchy of interconnect schemes is employed. Thin, short local interconnects provide on-chip connections within a chiplet or die. Thicker global interconnects span between blocks on the same die or between chiplets. Through-silicon vias (TSVs) transmit power, ground, and signals vertically through the die or between die in a 3D-IC stack.
"Communication between 2.5D chiplets is faster, higher bandwidth, and lower power than old-style PCBs," said Swinnen. "But it's also more expensive and many of the high-speed signals require full electromagnetic analysis."
As interconnect density increases, issues like IR drop and RC delay can limit performance. The industry is pursuing backside power delivery to reduce front-side routing congestion, maintain signal integrity, and ensure ample power delivery to transistors. However, this adds manufacturing complexity not yet fully addressed for high-volume production.
Taming the Protocol Zoo
Another dimension of interconnect complexity is the dizzying array of protocols and standards, which Schirrmeister dubs "the protocol zoo." Posner elaborates, "Within an SoC, you have legacy protocols like AMBA, but also evolutions like streaming interfaces, coherent hub interface (CHI) extensions, and more emphasis on network-on-chip (NoC) architectures."
Arteris has focused on expanding and scaling AMBA-based architectures across heterogeneous, multi-die topologies. "Most companies using RISC cores have gone to the CHI standard, but which version?" asks Schirrmeister. "The latest Arm cores use CHI-e, older ones used CHI-b - you have different capabilities in each version."
Ultimately, all of these disparate protocols must interoperate across the chiplet boundaries. "You have to ensure coherency by controlling who has the latest
memory data and other elements between chiplets," says Schirrmeister. "If one side speaks AXI, the other side needs to unpack those serial bitstreams back into AXI."
Emerging Chiplet Interconnect Standards
While some argued for a unified interconnect to rule them all, industry consensus favors a set of open standards tailored for different domains:
UCIe (Universal Chiplet Interconnect Express) for on-package, die-to-die communication
PCIe/CXL for off-package, rack/system interconnects
Ethernet for networking
"The industry needs interoperable standards to address multi-interconnect challenges for both scale-up and scale-out architectures," said Synopsys' Priyank Shukla. "We see complementary standards like UltraEthernet Consortium for scaled-out networking, AMD's Open Fabric and CXL for coherency, and UCIe emerging as the way to go for die-to-die connectivity within a package."
UCIe is rapidly gaining traction as the open standard for chiplet interconnects. "Even companies that control both ends are adopting standards like UCIe to benefit from collective industry knowhow," said Cadence's Mayank Bhatnagar. "There aren't enough engineers to design every chiplet interconnect permutation from scratch."
One critical unresolved challenge is testing these embedded interconnects after assembly. "You can't simply probe the interfaces with a needle like before," noted Andy Heinig from Fraunhofer IIS. "We need new solutions like on-chip monitoring and test capabilities if the bring-up fails or errors occur during operation."
Multi-Disciplinary Complexity
Developing robust interconnect solutions now requires a multi-disciplinary approach spanning digital, RF, photonics, power electronics, ASIC design, thermal, mechanical, and other domains - each with their own specialized design and analysis tools.
"High-speed digital, RF, photonics, power, ASIC design, thermal, mechanical - all these disciplines must be married together cohesively," said Mueth. "These domains are often interdependent, further compounding the design complexity."
Another layer of complexity is lifecycle management across design, test, and manufacturing. "Requirements, processes, and data have to be carefully managed since chiplets must perform in broader hierarchical systems," Mueth added. "There's an iterative element of top-down design and bottom-up verification required."
Mastering Interconnect Complexity
While developing interconnect solutions for heterogeneous integration is exponentially more complex than simply laying copper traces, it is essential to unlocking the benefits of chiplets and advanced packaging. Meeting this challenge requires industry collaboration on open standards, advanced multi-disciplinary design tools, innovative testing methodologies, and a cohesive multi-domain approach.
Interconnects have evolved from simple to mind-bendingly complex, but they remain integral to realizing tomorrow's computing architectures. By mastering interconnect design through the techniques outlined in this tutorial, chip architects and designers can pave the way for a new era of performance, efficiency, and semiconductor innovation.
Reference
[2] K. Heyman, "Interconnects Essential to Heterogeneous Integration," [Online]. Available: https://semiengineering.com/author/karen-heyman/. [Accessed: 21-Apr-2024].
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