Introducing the PhAST-Gate: A Novel All-Optical Silicon Photonics Logic Gate

Introduction

As the energy efficiency of digital silicon electronics reaches its limits due to the "End of Moore's Law", the demand for computing services continues to grow rapidly, driven by the widespread adoption of Artificial Intelligence and Machine Learning (AI/ML) technologies. This article introduces a new all-optical Silicon Photonics (SiP) logic gate concept, the "PhAST-Gate" (Photonic Absorption-Saturating Threshold Gate), which could help address the energy efficiency challenges in future AI/ML systems and other advanced computing applications.

The PhAST-Gate exploits the heterogeneous III-V Quantum Well-on-Si and Quantum Dot-on-Si photonic integrated platforms developed for integrated laser technology. The same III-V materials used for nonlinear (NL) saturable gain/absorption in lasers can be leveraged in the PhAST-Gate to provide the NL saturable absorption function for the logic operation.

The PhAST-Gate Concept

The PhAST-Gate concept comprises four key elements:

1. Binary Phase Shift Keying (BPSK) for data encoding

2. Coherent coupling of data signals with "photonic power rails" to enable gate-level gain for fanout and cascadability

3. A saturable absorbing element to provide the nonlinear response

4. A resonant cavity to enhance the nonlinear threshold and contrast ratio

In a photonic integrated circuit (PIC), an array of semiconductor optical amplifier (SOA) gain blocks would be integrated to provide a coherent power source for each gate, enabling high circuit density and complexity via a waveguide distribution network.

Figure 1(a) shows a modeled saturable absorber (SA) add-drop ring resonator response, exhibiting a smooth nonlinear characteristic with low loss and high contrast ratio. Figure 1(b) depicts the PhAST-Gate OR configuration with a micro-ring resonator (MR) containing the SA. The data inputs D1 and D2 are BPSK encoded, with equal amplitudes. The CW "pump" signals, P and P' (analogous to electronic "power" and "ground"), of opposite phase, are coupled at the input and output, enabling the fanout-of-2 needed for practical digital circuitry.

The modeled SA embedded within the resonator exhibits a sharp nonlinear thresholding response (Fig. 1(a)). Reversal of the phases of P and P' implements an AND gate, and a logical NOT is achieved by adding a π/2 section to flip the phase by π; thus, PhAST-Gate comprises a complete logic gate family.

Unlike some earlier proposed resonator-based gates, PhAST-Gate operates always on-resonance, using only the nonlinear absorption, allowing for a small cavity to achieve high gate density and speed. The threshold is determined by the input signal power relative to the saturation power of the SA element. Below the threshold, the quality factor (Q) is "spoiled" due to the absorption, and the transmission is near zero. Above the threshold, when the internal power of the resonator approaches the saturation power, the absorber quickly saturates, providing a rapid increase in Q and driving the gate to transparency.

Projected Performance and Potential Applications

Simulations using Lumerical Interconnect software demonstrate the potential of the PhAST-Gate concept to achieve both high contrast (~100:1) and high ON-state transmittance (>0.67), enabling embodiments that achieve 3-dB gain for a gate fanout-of-2.

Figure 2 depicts a 2-gate SR AND-OR latching flip-flop configuration (with Fabry-Perot resonator/SA elements) enabled by using the gate fanout for the feedback needed for latching. Such an element could serve as an all-photonic SRAM cell, where the bit is stored in the saturated state of the flip-flop, with one gate ON and the other OFF, or vice versa. This novel scheme requires no bistable resonator state or intervening electronic capacitance but, like electronic SRAM, if the power rails are energized, the state is held, making it a key enabler of true all-optical SRAM.

The PhAST-Gate concept achieves several key functionalities required for practical application, including fanout, lack of critical biasing, input/output isolation, cascadability, low power, and high speed. The authors estimate a gate footprint of ~200 μm^2, with a projected gate density of ~50,000 gates/cm^2 on a PIC, assuming 10% of the area is dedicated to gates and 90% for waveguide networks, SOA arrays, and other elements.

Under conservative estimation, the authors envision needing 1-10 Watts of coherent laser power distributed across the chip into the power rail, exploiting the same III-V on Si technology platform being developed by the DARPA LUMOS program. With existing SiP photodetector sensitivity performance, the PhAST-Gate output level must be > 20 μW, implying an optical requirement of ~ 50 μW. Assuming an insertion loss of 0.2 dB for each Y-junction, the power rail supply must be ~60 μW. With an SOA wall-plug efficiency (WPE) of 10%, the total electrical power required is ~0.6 mW. Assuming a 25 Gbps data rate, the energy requirement for the gate is approximately 25 fJ/gate-op, corresponding to ~30 W/cm^2 of total required electrical power at 50,000 gates/cm^2.

These projections suggest that the PhAST-Gate concept could provide a path to transformative expansion in SiP PIC complexity and application domain, enabling advanced computing architectures that benefit from maintaining data in the optical domain for improved speed and energy consumption.

Reference

[1] M. W. Haney, Y. Fainman, J. E. Bowers, D. Liang, S. Sunder, and S. Chandran, "All-optical Silicon Photonics-based Logic Gate," Information Sciences Institute, University of Southern California, Arlington, VA, USA; Electrical and Computer Engineering, University of California, San Diego, CA, USA; Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA; Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA; Global Foundries, Malta, NY, USA, 2024, pp. 1-6, doi: 979-8-3503-9404-7/24/$31.00 ©2024 IEEE.