Innovation and Development of Broadcom's 3.5D XDSiP Technology in Artificial Intelligence Computing

Introduction

In the field of artificial intelligence (AI) computing, traditional process scaling is facing limitations, while the industry's demand for high integration of logic, memory, and analog circuits in modern silicon-based packaging (SiP) continues to grow. To address these challenges, Broadcom has developed the 3.5D eXtreme Dimension SiP (XDSiP™) platform. By integrating 2.5D technology with 3D-IC using Face-to-Face (F2F) technology, this platform provides a novel solution for the development of next-generation custom accelerators (XPUs) and computing ASICs [1].

Figure 1: Broadcom’s 3.5D XDSiP platform technology, playing a role in advancing AI infrastructure with openness, scalability, and high efficiency.

Historical Progress and Increasing Complexity

The development of AI accelerators has spanned over a decade, with each generation bringing new capabilities and challenges. From its early stages in 2014 to anticipated advancements beyond 2026, this field has undergone continuous technological upgrades.

Figure 2: Evolution of Broadcom’s custom AI accelerators from 2014 to post-2026.

The complexity of consumer-grade AI XPUs has been growing exponentially, driven by multiple interrelated factors, including computing performance, network bandwidth, memory bandwidth, power delivery, thermal integrity, and mechanical reliability.

Figure 3: Growth trend of consumer-grade AI XPU complexity from 2014 to 2028, where the bubble size represents the increasing complexity of XPU designs.

Technical Challenges and Solutions

The semiconductor industry is facing significant challenges as traditional process scaling slows. While performance and power scaling continue to advance, logic and SRAM scaling have shown limitations.

Figure 4: Relationship between logic scaling, SRAM/IO scaling, performance, and power across different process generations, illustrating challenges in technology scaling.

The 3.5D XDSiP architecture addresses these challenges through an innovative approach, combining the advantages of 2.5D and 3D integration technologies, significantly improving performance, power efficiency, and form factor.

Figure 5: Transition from 2.5D XPU ASIC to 3.5D XPU ASIC, highlighting improvements in content density, package size, cost, and performance.

Implementation of Face-to-Face Technology

The Face-to-Face (F2F) technology in 3.5D XDSiP represents a breakthrough compared to traditional Face-to-Back methods, bringing substantial improvements in signal density, performance, and design flexibility.

Figure 6: Comparison of Face-to-Back and Face-to-Face 3.5D technologies, showing structural differences and performance advantages.

The F2F method achieves several key enhancements over traditional approaches: signal density between stacked dies is increased by seven times, signal performance is improved through shorter routing paths and lower parasitic loads, and greater flexibility is provided in the functional allocation of ASICs between top and bottom dies.

Current Applications and Future Development

Broadcom has developed multiple 3.5D XDSiP technology implementations to meet various computational needs and application scenarios.

Figure 7: Various implementations of 3.5D XDSiP custom XPU development, each with unique specifications and performance characteristics.

These implementations include configurations with different levels of 3D stacking, I/O chiplets, and memory solutions. The first implementation features dual 3D stacking with twelve HBM3 modules in a 100x100 package, while other versions incorporate different stacking, chiplet, and memory technologies based on specific performance requirements.

Figure 8: Key achievements of Broadcom’s 3.5D XDSiP technology, including industry innovation, scaling capabilities, and development roadmap.

Technical Advantages and Market Impact

The 3.5D XDSiP technology has achieved significant improvements across multiple performance metrics. In terms of interconnect density, signal density has increased by seven times compared to previous solutions. By replacing planar die-to-die PHY with 3D HCB technology, die-to-die interface power consumption has been reduced by ten times. Additionally, this platform significantly reduces latency between computing, memory, and I/O components in 3D stacking.

The compact packaging enabled by this technology results in a smaller interposer and package size, reducing costs and improving package warpage control. Notably, this technology overcomes previous scaling limitations, allowing the integration of over 6000 mm² of silicon area and 12 HBM modules within a single package.

Future Outlook

As AI computing continues to evolve, the demand for more powerful and efficient solutions will persist. Broadcom’s 3.5D XDSiP technology is scheduled for production in early 2026, marking a significant step in addressing these challenges. By combining advanced packaging technologies with innovative design methodologies, this platform lays the foundation for future AI computing solutions. The impact of this technology extends beyond current applications, setting a new standard for AI acceleration and computing architectures. The 3.5D XDSiP platform represents a major milestone in the evolution of AI computing architectures, driving new capabilities and applications forward.

Reference

[1] Broadcom Inc., "3.5D XDSiP Platform Technology - ASIC Products Division," Broadcom Technical Documentation, Dec. 5, 2024.