IEDM2024|EDA Support for Scalable Disaggregated Systems

Introduction

In the rapid evolution of semiconductor design, electronic design automation (EDA) plays a central role in enabling the development of modern scalable disaggregated systems. This paper explores the challenges, methodologies, and solutions in the context of 3DIC and system technology co-optimization (STCO) [1].

Evolution of EDA and System Architectures

The semiconductor industry has progressed from traditional application-specific integrated circuit (ASIC) design methodologies to more complex disaggregated systems. As shown in figure 1, ASIC place and route (P&R) has evolved significantly from hand-drawn schematics before 1970 to modern design technology co-optimization (DTCO). This evolution demonstrates how EDA tools have adapted to increasingly complex design requirements.

Figure 1: Evolution of ASIC design tools and methodologies from before 1970 to post-2015, highlighting the transition from manual to automated flows.

System architecture has evolved to accommodate new market demands and technological capabilities. Figure 2 illustrates the STCO hierarchy, showing the complex relationships among various system layers, from process technology to application workloads.

Figure 2: System Technology Co-Optimization (STCO) hierarchy and its impact on performance, power, area, and cost (PPAC).

Disaggregated Architectures and Challenges

Disaggregated architecture represents a fundamental shift in system design. It is more than just a change in chip partitioning—it affects every discipline in silicon engineering. Key challenges include:

1. Main-band interconnect fabric architecture

2. Side-band fabric architecture (DFX, PM, Clock)

3. SoC topology and product configuration

4. Integration floor planning, power delivery, and thermal considerations

5. Test, verification, and manufacturing requirements

Figure 3: Conceptual view of disaggregated architectures and the diverse design considerations, metaphorically illustrated as a pizza-slicing approach.

3D Interconnect Types and Implementation

Modern 3D systems employ various interconnect technologies:

1. Package-side bumps

2. Micro-bumps

3. Through-silicon vias (TSV), trough-dielectric vias, and through-mold vias (TMV)

4. Top metal power grid

5. Top metal signal routing

Figure 4: Different types of 3D interconnect technologies and their implementation in modern semiconductor design.

Optimization and Analysis Techniques

A systematic approach to 3D design optimization includes several key steps:

1. Early design space exploration

2. Initial bump placement

3. Bump-to-flip-flop distance analysis

4. Module alignment optimization

Figure 5: Heatmap visualization used to analyze and optimize bump-to-flip-flop distances in 3D designs.

The optimization process includes careful consideration of metal layer scaling and area utilization. Figure 6 illustrates how different metal layer configurations impact performance and power metrics.

Figure 6: Relationship between design area scaling and various performance metrics in 3D implementations.

Performance, Power, and Area (PPA) Analysis

PPA analysis is critical to evaluating the effectiveness of 3D implementations. Key findings from the BZM test chip study include:

1. An average path delay reduction of 9% across over 100,000 register-to-register paths

2. Two fewer metal layers required on both top and bottom wafers

3. Significant improvement in area utilization and power efficiency

Figure 7: Trade-offs in PPA for 3D implementations and their impact on overall system performance.

Future Directions and Challenges

The future of EDA for disaggregated systems focuses on several key areas:

• Automated bump planning and optimization

• Improved TSV placement and alignment

• Enhanced top-metal routing for power and signal networks

• Advanced signoff tools for early prototyping support

• Integrated multi-physics analysis capabilities

Figure 8: Integrated methodology for 3D IC design and validation, emphasizing the importance of a unified design environment.

As system complexity increases, the need for sophisticated automation and optimization techniques becomes even more critical. The focus remains on achieving peak performance in increasingly complex 3D integrated systems while managing power and area efficiency.

A comprehensive approach is required to integrate all aspects of design—from architectural planning to physical implementation—ensuring that the final design meets the stringent demands of modern applications while maintaining manufacturability and reliability.

Reference

[1] Evolution of ASIC design tools