Minimizing power, energy, or thermal impacts requires a concerted approach throughout the entire design, development, and implementation flow.
The power consumption of a device is influenced by every stage of the design, development, and implementation process, but identifying opportunities to save power no longer can be just about making hardware more efficient.
Tools and methodologies are in place for most of the power-saving opportunities, from RTL down through implementation, and portions of the semiconductor industry already are using them. Both are considered mature, and so are the standards for defining power intent.
Huge opportunities still remain for additional power and energy savings, but many of those involve questioning system-level decisions that have been blindly accepted for generations and many implementation nodes. Some of those decisions need to be reconsidered because they are preventing the construction of larger and more complex designs.
“There are three horsemen in the mix — power, energy, and thermal,” says Rob Knoth, product management director in the Digital & Signoff Group at Cadence. “They’ve always been there, and power is probably the most prominent, but energy has come to the forefront over the last few years. Now we’re seeing thermal show up. All of them are interesting because you can attack them at specific points in your flow with specific tools.”
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