Compact Silicon Photonic Interconnects: A Game-Changer for High-Speed Data Transfer

Introduction

In today's data-driven world, the demand for high-speed and energy-efficient data transfer has never been higher. Conventional electrical interconnects are rapidly reaching their limits, struggling to keep up with the insatiable appetite for bandwidth. This is where silicon photonic interconnects come into play, promising a revolutionary solution that can potentially replace electrical interconnects at on-board and in-package length scales.

Silicon photonics is an attractive platform for this application due to its compact waveguide bends, scalability, maturity, and the ability to integrate other photonic materials for efficient photodetectors, modulators, and lasers. This article will delve into the cutting-edge technology of silicon photonic interconnects, exploring their architecture, key components, and the promising path toward compact and energy-efficient communication links.

Photonic Architecture

The photonic architecture of a silicon photonic transceiver serves as a milestone toward achieving aggregate capacities of 1 Pbps with an energy consumption of 0.1 pJ/bit at a range of ambient temperatures. Figure 1 illustrates this architecture, where a 20-wavelength quantum dot mode-locked laser (QD-MLL) comb source has its outputs coupled to separate 1 Tbps silicon photonic PICs.

Figure 1: Photonic architecture for a high-capacity silicon photonic link (top) and a cross-section cartoon of the photonic and electronics packaged together via 3D integration (bottom).

Microring Modulators: The Heart of the Transceiver

One key technology that has emerged from silicon photonics is the microring modulator (MRM). These resonant-based structures can modulate a single wavelength out of a summation of multiple wavelengths, eliminating the need for multiplexers in the system.

In the transmitter (TX) portion of the PIC, the even and odd channels of the comb source are separated to different ring banks. Each bank has 10 MRMs that operate at 26.4 Gbps NRZ with a 5.6% forward error correction (FEC) overhead. The modulated odd and even comb lines are then interleaved together, and a shallow 210 MHz clock signal is encoded onto all channels for optical clock transmission via a variable optical attenuator (VOA).

The 500G lanes pass through quantum dot semiconductor optical amplifiers (QD-SOAs) before being polarization multiplexed onto a single 1T port for propagation over polarization-maintaining (PM) fiber.

Receiver Architecture

On the receiver (RX) side, the PIC polarization demultiplexes the two 500G lanes. A small fraction of the power of each channel is sent to a photodiode (PD) that detects the clock signal. The rest of the power is deinterleaved, and each individual 25G channel is demultiplexed by a corresponding WDM ring resonator filter with a high-speed PD receiver on its drop port.

The RF driver for the transceiver is flip-chip bonded directly to the PIC to conserve energy, while the ring resonator filters in the PIC require circuitry to actively align themselves to the QD-MLL comb lines, achieved through 3D integration to reduce footprint.

Quantum Dot Mode-Locked Laser Comb Source

A crucial component of this architecture is the QD-MLL comb source, which replaces an array of single-wavelength DFB lasers, eliminating the need for a multiplexer with its additional insertion loss.

Figure 2: (a) Picture of packaged QD-MLL with two fiber outputs. (b) Highly efficient comb spectrum generated by QD-MLL with 20 comb lines above −5 dBm power.

By implementing quantum dots (QDs) as the active region, these lasers achieve wall-plug efficiencies (WPEs) as high as 12%, with a flat comb spectrum that can be produced at elevated temperatures of 60°C. An example comb spectrum used for data transmission is shown in Figure 2(b), with each side capable of generating the same spectrum and power level. The comb spectrum contains 20 lines with power above -5 dBm per facet and consumes only 129 mW, leading to an energy consumption of 65 fJ/bit when used as a source for two 1 Tbps systems.

Silicon Photonic Integrated Circuit

The heart of the transceiver is the 1 Tbps silicon photonic integrated circuit (PIC), which is fabricated at a 300 mm silicon photonics foundry. Figure 3 shows a micrograph of this PIC, with a small 1.7 mm x 3.2 mm footprint that allows for the production of multiple 1 Tbps cells to increase the aggregate capacity per chip. The pad pitch of 36 microns within the RF driver pad region yields a local area bandwidth density in the high-speed photonics region of the PIC of 5.3 Tbps/mm^2.

Figure 3: Micrograph of the 1 Tbps silicon photonic integrated circuit.

Microring Modulator Performance

The performance of the MRMs is crucial for the overall efficiency of the system. Figure 4 highlights the DC performance of these MRMs. Nonlinear losses and self-heating due to power buildup inside the cavity limit the incident power on the ring near −5 dBm before the resonance shape distorts and redshifts.

Figure 4: Ring modulator power handling (top) and phase shifter voltage sweeps (bottom left). Wafer map generated per reticle of how many rings in a bus of 10 could align to the QD-MLL spectral grid (bottom right).

The resonance is also redshifted with a DC electro-optic (EO) phase shift by reverse biasing a p-n junction within the cavity. This EO tuning shifts the resonance by 52 GHz over a 5V span, which can be used to correct for wavelength drifts that can be incurred from temperature and fabrication deviations. The EO DC tuning strength of these phase shifters is enough to allow for all 10 rings in a bus to align to the QD-MLL odd-even channel separation in half of all reticles across half of a 300 mm wafer at a fixed temperature without the need for integrated heaters that would consume more power.

Single-Channel Modulation Experiments

To validate the performance of the MRMs, single-channel modulation experiments were conducted. Figure 5 shows the experimental setup and results. The QD-MLL output passes through an MRM driven by an arbitrary waveform generator (AWG) producing a 27 Gbps NRZ signal with a VPP = 1V that is pre-emphasized to mitigate cable losses. The optical signal is passed through a commercial QD-SOA and then through a tunable optical filter to remove the unmodulated comb lines. The modulated line is coupled into a PD that has a low-noise amplifier (LNA) on its backend, connected to an oscilloscope.

Figure 5: Link experiments and resultant eye diagrams. Boxed elements indicate variations from the original experimental setup.

The achieved bit error rate (BER) in the preliminary experiment of 2.9E-5 is close to the system's FEC threshold of 1.3E-5. However, this simplified experiment lacks a deinterleaver, causing three QD-MLL comb lines to be coupled into the ring instead of one. This excess input power causes self-heating and degrades signal integrity.

In the secondary iteration, where the QD-MLL is filtered down to a single carrier before passing into the MRM to prevent self-heating, a worse BER is observed, likely due to the extra filter loss. Substituting the QD-MLL with a commercial tunable laser with the same wavelength and power conditions achieves a similar BER, indicating that a QD-MLL comb source with −5 dBm per line should be sufficient for a 1 Tbps link.

Energy Consumption Projections

One of the key advantages of silicon photonic interconnects is their potential for ultra-low energy consumption. Figure 6 projects the energy consumption of a 1 Tbps link based on the conditions used in the single-wavelength demo (0.76 pJ/bit) and if the losses in this experiment matched the 1 Tbps link (0.39 pJ/bit).

Figure 6: Energy budgets for a 1 Tbps system utilizing a QD-SOA.

Beyond lower losses than were achieved in the single-wavelength demonstration, a 1 Tbps link would benefit from a flip-chip bonded driver chip instead of RF probing, lower input power into the ring modulators, and ring stabilization circuitry. Access to avalanche photodiode (APD) receivers with a modest gain-bandwidth product of 200 GHz would enable removing the QD-SOAs, which could realize energy consumption as low as 0.21 pJ/bit.

Electronic-Photonic Integration

To fully realize the potential of silicon photonic interconnects, electronic-photonic integration is crucial. The electronic IC (EIC) design consists of two EICs, the driver and controller, each in 65nm CMOS.

The TX on the driver EIC provides the data traffic using on-chip PRBS sources (2^31 − 1), where the PRBS sequence is decimated by 32, allowing 32 independent phase-shifted paths. The on-chip serializer converts 8 channels of the 3.375 Gbps PRBS bitstream, using a pipelined latch-based approach, to drive the ring modulator at 27 Gb/s. An injection-locked oscillator synchronized to the on-chip PLL provides the 8 phases of clocks required for serialization.

On the RX side, a 27 Gbps TIA based on inverters with a DC offset correction loop converts the PD current into a digital signal. The reference clock of the PLL on the TX side is sent as an amplitude-modulated wave, recovered, and used as a reference for the RX PLL to enable deserialization of the data.

The drift of the ring modulator bias is corrected using a control EIC, which receives the optical signal via a monitor PD. The current is digitized using a VCO-based ADC and compared to a desired setting. The error signal is then passed through a digital loop filter and converted into a ΔΣ bit stream and converted to a high voltage signal (0-to-6V) via a level shifter and filtered to yield the bias voltage for the modulator.

Figure 7 validates that the control chip can successfully DC bias an MRM, read its monitor PD signal, lock the monitor PD signal to a set value, and distinguish between locking on the red (long-wavelength) and blue (short-wavelength) sides of the resonance.

Figure 7: Experimental results of DC biasing a ring modulator with the control EIC as DAC levels are stepped (left). The monitor PD signal is read and converted into an ADC code (middle). The locking functionality is verified by closing the loop (right).

Conclusion

Silicon photonic interconnects represent a promising path toward compact and energy-efficient communication links that can compete with electrical interconnects at short lengths. This work outlines the key components, architecture, and experimental validation of a 1 Tbps silicon photonic transceiver, paving the way for future developments in this field.

Future work includes completing electronic-photonic packaging, conducting WDM experiments, introducing avalanche photodiode receivers, increasing capacity per module, and integrating the comb source. With continued research and development, silicon photonic interconnects have the potential to revolutionize high-speed data transfer, enabling unprecedented levels of bandwidth and energy efficiency in a compact form factor.

Reference

[2] Netherton, M. Dumont, Z. Nelson, J. Jhonsa, A. Mo, J. Koo, D. McCarthy, N. Pestana, S. Deckoff-Jones, C. Poulton, M. Frankel, J. Bovington, L. Theogarajan, and J. Bowers, "25.1 Short-Reach Silicon Photonic Interconnects with Quantum Dot Mode Locked Laser Comb Sources," in IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, USA, 2024.