Introduction
The demand for high-speed data transmission and processing is rapidly increasing due to emerging technologies such as artificial intelligence (AI), 5G, edge computing, cloud data centers, autonomous vehicles, and wearable technology. To meet these demands, the semiconductor industry is moving towards heterogeneous integration, which combines different components and technologies onto a single package. One particular area of focus is co-packaged optics (CPO), which involves the heterogeneous integration of photonic integrated circuits (PICs) and electronic integrated circuits (EICs).
Silicon Photonics
Silicon photonics is the integration of optical components onto a silicon substrate using complementary metal-oxide-semiconductor (CMOS) technology. This integration enables the generation, manipulation, and detection of light on a silicon chip, facilitating high-speed data transmission and processing. Figure 1 shows examples of silicon photonics devices, including a hybrid silicon laser and an Intel silicon photonics chip.
Optical Transceivers
Optical transceivers are key components in optical transmission systems, converting electrical signals to optical signals and vice versa. They consist of a transmitter optical sub-assembly (TOSA) and a receiver optical sub-assembly (ROSA). The TOSA contains a laser diode and driver, while the ROSA includes a photodiode, transimpedance amplifier (TIA), and optical interface. Figure 2 illustrates the components of an optical transceiver and the integration of a PIC and an EIC.
Packaging Options
There are several packaging options for integrating optical transceivers, including pluggable transceivers, on-board optics (OBO), near-package optics (NPO), and co-packaged optics (CPO). Figure 3 shows the evolution of these packaging approaches over time, highlighting the transition from pluggable transceivers to CPO for higher performance and integration.
Co-Packaged Optics (CPO)
CPO involves the heterogeneous integration of a PIC and an EIC onto a single package substrate. This integration enables high-speed data transmission and processing by combining the advantages of optical and electrical components. Figure 4 illustrates different approaches to integrating a PIC and an EIC in a 2D heterogeneous integration scheme using various interconnect technologies, such as micro-bumps, copper-copper hybrid bonding, and through-silicon vias (TSVs).
2D Heterogeneous Integration
Figures 5 and 6 depict examples of 2D heterogeneous integration of an ASIC switch, a PIC, and an EIC. These approaches leverage technologies like micro-bumps, TSVs, and silicon bridges to achieve high-performance data transmission and processing.
3D Heterogeneous Integration
For even higher levels of integration and performance, 3D heterogeneous integration techniques can be employed. Figures 7 and 8 illustrate various 3D heterogeneous integration approaches, including face-to-face integration of a PIC and an EIC, and the integration of an ASIC switch, a PIC, and an EIC on a co-packaged substrate with TSVs or organic interposers.
Silicon Bridges and Embedded Multi-die Interconnect Bridges (EMIBs)
To facilitate high-density interconnections between chiplets in heterogeneous integration, silicon bridges and EMIBs are employed. Figures 9 and 10 show examples of silicon bridges and EMIBs from various manufacturers, including Intel, IBM, and Apple.
Advanced Packaging Technologies
As the demand for higher performance and integration continues to grow, advanced packaging technologies are being developed. One such technology is TSMC's CoWoS (Chip on Wafer on Substrate) architecture, which utilizes reconstituted interposers (RIs) composed of local silicon interconnects (LSIs) and fan-out redistribution layers (RDLs). Figures 11 and 12 illustrate TSMC's CoWoS and CoWoS-L architectures, highlighting the use of LSIs and RIs for high-performance heterogeneous integration.
Glass Substrates for Co-Packaged Optics
To address the limitations of organic substrates and enable further scaling of transistors in a package, Intel has announced the development of glass substrates for next-generation advanced packaging. Glass substrates offer superior properties, such as ultra-low flatness, better thermal and mechanical stability, and higher interconnect density. Figures 13 and 14 showcase Intel's glass substrate technology, including a fully functional test chip and a glass panel.
Heterogeneous Integration on Glass Substrates
Figures 15, 16, and 17 illustrate potential approaches for heterogeneous integration of EICs and PICs on glass substrates. These approaches leverage the unique properties of glass substrates, such as the ability to integrate glass waveguides and through-glass vias (TGVs), enabling higher interconnect densities and improved power delivery and signal routing.
Challenges and Considerations
While glass substrates offer significant advantages, there are also challenges to consider. These include higher production and packaging costs, initial yield issues, the need for a viable ecosystem (including tooling and material suppliers), and the necessity for outsourcing test and assembly processes.
Summary
Co-packaged optics (CPO) represents a critical advancement in heterogeneous integration, enabling the combination of photonic integrated circuits (PICs) and electronic integrated circuits (EICs) onto a single package substrate. This integration facilitates high-speed data transmission and processing, addressing the growing demands of emerging technologies such as AI, 5G, edge computing, and data centers.
Various approaches to CPO have been explored, including 2D and 3D heterogeneous integration techniques, leveraging technologies like micro-bumps, TSVs, silicon bridges, and EMIBs. Additionally, advanced packaging technologies, such as TSMC's CoWoS and CoWoS-L architectures, are being developed to further enhance performance and integration capabilities.
Looking ahead, Intel has introduced glass substrates as a promising solution for next-generation advanced packaging. Glass substrates offer superior properties, including ultra-low flatness, better thermal and mechanical stability, and higher interconnect density, enabling the continued scaling of transistors in a package beyond 2030.
While challenges exist, such as higher costs, yield issues, and ecosystem development, the semiconductor industry is actively working to overcome these obstacles and unlock the full potential of co-packaged optics and glass substrate technologies for future data-centric applications.
Reference
J. H. Lau, "Co-Packaged Optics: Heterogeneous Integration of Photonic IC and Electronic IC," presented at the IEEE Electronic Packaging Society - Central Indiana Chapter, Unimicron Technology Corporation, March 5, 2024.
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