AIM Photonics PDK Design Methodology - Device Development and Integration

Terence S.-Y. Chen

Latitude Design Systems

Introduction

Silicon photonics is an emerging technology poised for high volume growth in applications such as datacom, telecom, lidar and optical computing. As silicon photonics transitions from research to commercialization, there is a critical need for mature design enablement methodologies and tools that can improve design efficiency and time-to-market. Foundries like AIM Photonics have invested in developing robust silicon photonics process technologies.

This white paper evaluates AIM Photonics' design enablement methodology based on their recent publication. The methodology is analyzed to identify strengths and potential areas of improvement. Comparisons are made to CMOS/RF foundry best practices and capabilities of PIC Studio, a commercial photonic IC design platform from Latitude Design Systems. Recommendations are provided on how AIM Photonics could enhance their design methodology to better support fabless photonic IC designers.

AIM Photonics was established in 2015 as part of a US government initiative to advance integrated photonic technology manufacturing and innovation. As both a research consortium and a silicon photonics limited-volume production facility, AIM Photonics has invested significantly in silicon photonic process development and design enablement at their TAP facility located in Albany, NY.

This white paper provides an expert assessment of AIM Photonics' design methodology based on their detailed publication. The workflow contains five main elements:

1. Component development

2. Test site layout

3. Measurement infrastructure

4. Compact modeling

5. PDK integration

Each stage of the methodology is analyzed, including the use of simulation tools like Lumerical MODE and FDTD, automated layout generation, on-wafer testing, and statistical compact modeling. Comparisons are made to established practices in CMOS and RF technology enablement.

Figure 1. Design Enablement Flow for Silicon Photonic Technology (Source: AIM Photonics)

Additionally, the AIM Photonics approach is compared with capabilities offered by PIC Studio, a commercial integrated design platform from Latitude Design Systems tailored to photonic IC needs. Recommendations are presented on how AIM Photonics could adopt certain best practices from electronic design automation and enhance their methodology by leveraging commercial photonic IC design tools. AIM Photonics works with Synopsys to provide PDKs with end-to-end capability.

Figure 2. Design Enablement Flow for Silicon Photonic Technology

AIM Photonics Design Enablement Methodology

1. Component Development Flow The component development flow is based on using simulation tools like Lumerical MODE and FDTD to design and optimize photonic components. A key strength is the availability of a process stack file that encodes critical fabrication data like layer thicknesses and doping profiles. This allows component designs to accurately reflect the manufacturing process. An example is presented of simulating a carrier injection microring modulator. Multiple variations are included in layouts to enable statistical modeling. The component simulation methodology follows standard practices used in photonic design. However, there are opportunities to further improve accuracy. Most photonic components exhibit fabrication variability that can impact performance distributions across a wafer. Capturing these effects requires large-scale statistical simulations using Monte Carlo analyses. Performing such simulations and extracting parameterized compact model templates would enable variability to be incorporated directly into circuit-level simulations for reliability assessment. This practice has been widely adopted in electronics.
   

Figure 3. Left: Data processing for analysis and compact modeling, Right: Waveguide statistical and corner model illustration. Note：‘sns’: extreme case representing a short-narrow-higher loss (slow) waveguide ；‘tws’: tall-wide-higher loss (slow) waveguide (Source: AIM Photonics)

1. Test Site Layout Automation An automated layout generation framework is described that produces test sites for measurement from spreadsheet-based inputs. Standardized padsets for on-wafer probing are employed. The use of automation and padset standardization are positives that improve efficiency. The input spreadsheets controlling layout can also be utilized for measurement software, enabling continuity from design to test. Further layout automation enhancements could be made by incorporating additional checks on the manufacturability of automatically generated designs. For example, modern electronic design automation performs design rule checking, layout versus schematic comparison, and dummy fill as standard parts of layout generation. Performing these steps would improve yield and reduce mask defects.

2. Measurement Infrastructure The measurement infrastructure utilizes automated wafer-scale probing for data collection. Grating couplers allow light to be coupled from a fiber array for hands-off testing. Statistical data is gathered on multiple dies across wafers from different lots. This methodology enables efficient characterization of fabrication variability. While suitable for initial enablement, the grating coupler approach has limitations in bandwidth, wavelength range and polarization dependence. As the technology matures, enhancing the methodology to support edge coupling measurements would improve accuracy. This requires precision alignment for edge coupling, but removes losses and distortions from grating effects.
   

Figure 4. Measurement setup for large-scale, on-wafer automated measurements at O and CL-Band

1. Compact Modeling The statistical data collected by measurements is processed to create parameterized compact models. Examples are given of extracting waveguide models that include fabrication variability corners. The models target established photonic design platforms like Lumerical and Cadence. The compact modeling methodology could be improved by developing standardized model formats to enable easier porting of models between different tool vendors. Model validation procedures should also be enhanced to qualify models for circuit design prior to PDK release. Statistical simulation techniques leveraged in analog/RF modeling are applicable.

2. PDK Integration and Build The final PDK integration brings together component libraries, layout support and compact models into EDA vendor design environments like Cadence and Synopsys. DRC rule decks are also provided. PDKs are offered in both commercial tools and open-source platforms like KLayout.

While covering the major requirements, the PDK integration process could benefit by implementing more rigorous photonic PDK checklists prior to release. For example, the Si2 Compact Model Coalition has developed detailed model qualification procedures and release checklists that improve quality. Developing equivalent best practices for photonic PDKs would enhance designer productivity.

Perspective on PIC Design Platforms

In addition to the AIM Photonics approach focused on foundry-specific PDK enablement, there are emerging commercial design platforms seeking to provide unified tools for photonic IC design. PIC Studio from Latitude Design Systems is one such integrated suite comprising schematic capture, layout, and circuit/system-level simulation. A key benefit of integrated platforms is enabling design portability across different foundry processes.

By working closely with foundries like AIM Photonics to ensure comprehensive PDK support, integrated design suites can give designers flexibility to switch manufacturing processes without redoing designs. Platforms like PIC Studio also allow co-simulation of electronics and photonics within the same environment. As silicon photonics usage grows across different application domains, use of integrated design platforms may gain traction due to improved design reuse.

Conclusion

As silicon photonics technology continues maturing from research to commercial deployment, comprehensive and robust design enablement methodologies will be critical to ensuring the success of fabless photonic IC developers. This white paper has provided an expert assessment of the design methodology developed by AIM Photonics for their 300mm wafer manufacturing process.

AIM Photonics works with Synopsys to provide PDKs with end-to-end capability. Their methodology establishes a solid baseline covering key aspects like component development, automated layout, measurement data, and compact modeling.

To further advance photonics design enablement, it is recommended that all silicon photonics pilot lines and foundries consider leveraging capabilities offered by Latitude Design Systems's PIC Studio platform. PIC Studio provides a complete integrated design flow from schematic entry to physical verification, helping foundries deliver comprehensive PDKs.

Key features of PIC Studio that can augment foundry design methodologies include:

• PhotoCAD layout tool with connectivity to photonic solvers like FDTD/EME for verification

• pSim circuit simulator supporting co-simulation with major Spice/RF Spice simulators

• Advanced SDL for automatic layout generation from schematics (patent pending)

• Calibre integration for physical verification and DRC

• By leveraging PIC Studio's integrated photonics design flow and working closely with foundries like AIM Photonics, Latitude Design Systems can help enable end-to-end PDK development encompassing schematic, layout, and critical verification steps. This will further enhance silicon photonics design infrastructure to meet the needs of fabless photonic IC developers.

Figure 5. The existing list of wafers fab PDKs in PIC Studio, additionally, PIC Studio also supports one-click import of new wafer fab process layer definitions, enabling the rapid creation of new PDKs