Introduction
In the rapidly evolving landscape of semiconductor technology, the Bunch of Wires (BoW) protocol stands out for its capability to facilitate efficient die-to-die (D2D) parallel interfaces. This tutorial delves into the recent advancements and future directions of BoW, focusing on its applications in Optical, Memory, and IoT interfaces. This is based on insights from industry leaders like Shahab Ardalan, Kevin Donnelly, and Kash Johal, who presented their perspectives at a recent technical conference.
BoW Key Features
BoW's open PHY and Link Layer specifications are designed to support high-performance D2D interfaces. Key performance metrics include data rates up to 32Gb/s per line, energy efficiency below 0.5pJ/bit, and latency under 8ns. BoW's compatibility with various packaging and IC processes makes it a versatile solution across different cost and performance design points.
Evolution to BoW 2.1
To foster the Open Chiplet Economy, BoW is being enhanced to meet the demands of new applications, particularly in AI, Edge, and IoT domains. The upcoming BoW 2.1 release will introduce specification extensions in three critical areas: Optical, Memory, and IoT.
Higher Performance for AI and Edge Applications
BoW 2.1 aims to deliver higher performance required for AI and edge applications. This includes improvements in data transfer rates and reductions in power consumption, making it a robust solution for high-demand environments.
Lower Cost for IoT Applications
For IoT applications, the focus is on reducing costs while maintaining performance. This involves optimizing the specifications to ensure low power consumption and minimal area usage, which are crucial for IoT devices.
Optical Interconnect for D2D Interfaces
Motivation for Optical D2D Interface
Integrating optical engines (electrical-to-optical and optical-to-electrical) within the ASIC package offers several advantages, such as reduced latency and enhanced data integrity.
Direct Driving Optical Engines Using BoW
The approach involves directly driving the optical engine using existing BoW IP without the need for retiming at the optical chiplet. This simplifies the design and enhances performance.
Memory Interfaces and the “Memory Wall”
Challenges with the Memory Wall
The "Memory Wall" is a significant bottleneck in the performance of Generative AI ASICs, driven primarily by DRAM bandwidth limitations. BoW interfaces can dramatically improve memory bandwidth per millimeter for ASICs, addressing this challenge effectively.
D2D Signaling Technology Types
BoW 1.0, UCIe 1.1, and the forthcoming BoW 2.0 offer various solutions for D2D signaling. Each iteration brings improvements in bandwidth, power efficiency, and latency.
Example D2D Use Cases for Memory
DDR5 DIMMs: Offers read bandwidth of 128 GB/s with a read/write bandwidth ratio of 2x.
HBM4 DRAM: Supports read/write bandwidth of 2 TB/s with ECC traffic and control overhead of 25%, utilizing a beachfront of less than 10mm.
For Logic-to-Logic Interfaces
PHY Changes: Asymmetric read vs. write bandwidth may be retained.
Link Layer Changes: New interface profiles and possibly bus variants to support asymmetry.
Configuration Documentation: Specific to each protocol.
For Logic-to-Memory Interfaces
PHY Changes: Dynamic bidirectional communication.
Link Layer Changes: New profiles for each memory type.
Configuration Documentation: Specific to each memory type.
IoT and Sensors: Tailored Solutions
Requirements for IoT Interfaces
IoT applications demand low-cost, low-power solutions with simplified device requirements. BoW addresses these needs by:
Reducing area and power consumption.
Supporting flexible RX and TX configurations without the need for PLLs.
Ensuring scalability from low to high clock rates (500 MHz to 1 GHz and beyond).
Benefits and Drawbacks of IoT Proposals
Advantages
Optimized synchronization and signal integrity due to close proximity of data buses to the clock.
Symmetrical design enabling shared layouts between TX and RX PHYs.
Dual-purpose TX and RX PHYs for flexible signaling schemes.
Simplified device setup with reduced PLL requirements, lowering power and cost.
Drawbacks
The simplified design might limit some advanced functionalities required by high-performance applications.
Conclusion
BoW continues to evolve, offering significant advancements in performance and cost-efficiency for Optical, Memory, and IoT applications. With ongoing work on the BoW 2.1 specifications, the community is invited to participate and contribute to this open standard. The forthcoming release in 2024 promises to enhance interoperability and support new applications, driving innovation in the semiconductor industry.
Reference
[1] S. Ardalan and L. Giuliano, "Tools for the Open Chiplet Economy: Standardized Metrics for Chiplet Interconnect (PHY) Comparison," presented at the Open Compute Project (OCP) Global Summit, San Jose, CA, Mar. 2024.
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