Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond

Introduction

As semiconductor devices continue to shrink, balancing performance and power consumption become increasingly challenging. When transistor sizes reach 2nm and below, nanosheet technology has gradually replaced FinFET architecture. This article explores innovative methods to implement multi-threshold voltage solutions through selective layer thinning [1].

Figure 1 illustrates the roadmap of CMOS technology evolution from FinFET to Nanosheet architecture, highlighting the trend of continuous transistor scaling.

Compared with conventional FinFET designs, the nanosheet transistor architecture offers several advantages, including a larger effective width per effective device footprint and superior electrostatic control. These benefits translate into better power-performance characteristics. With the advancement of extreme ultraviolet (EUV) lithography, especially high-NA EUV, nanosheet technology provides more flexible design options to optimize performance and reduce power consumption.

Figure 2 shows the typical design layout in Nanosheet technology, where high-performance logic standard cells require wider nanosheet widths, while high-density designs demand tighter N-P spacing.

Challenges in Multi-Threshold Voltage Integration

One of the primary challenges in implementing multi-Vt solutions in nanosheet technology arises from its complex structure. The combined effects of the spacing between stacked nanosheets (Tsus) and gate length (Lg) pose unique integration challenges. Previous solutions used Tsus pinch-off (TPO) to avoid soft mask issues within Tsus, but 2nm and future nodes require new approaches for robust multi-Vt integration.

Figure 3 illustrates a typical metal gate patterning process, showing how the removal of metal from within Tsus in nFETs affects the blocking mask profile.

A key aspect of multi-Vt integration is managing the metal gate boundary (MGB) between NFET and PFET regions. For 2nm technology nodes, the widest nanosheet width is around 40-50nm, while the tightest N-P spacing is less than 40nm. These dimensional constraints make metal undercut control particularly challenging in the multi-Vt integration process.

Selective Layer Thinning Solutions

To address these challenges, researchers have developed two innovative approaches: Selective Layer Thinning 1 (SLR1) and Selective Layer Thinning 2 (SLR2).

Figure 4 illustrates how undercut depends on metal thickness, along with the impact of plasma damage during the thin layer patterning process.

SLR1 is specifically designed to control the N/P boundary by addressing the undercut issue in thin-layer patterning of the TPO scheme. This method includes a new etching process that effectively minimizes plasma damage to the gate dielectric layer, which is critical for maintaining device performance and reliability.

Figure 5 presents the optimized results of SLR1, showing significant improvements in dielectric properties achieved through the new process.

SLR2, on the other hand, focuses on controlling the N/P boundary during the integration of thick work-function metals (WFM). This technique is particularly important for achieving low-threshold voltage devices while maintaining proper metal gate profiles.

Figure 6 illustrates how gate length scaling impacts metal gate patterning, along with the proposed multi-WFM deposition method.

Performance Optimization and Results

The implementation of these selective layer thinning techniques has achieved remarkable success in realizing multiple threshold voltage options. By combining bulk-free multi-Vt and metal-based Multi-Vt approaches, researchers have successfully achieved four pairs of threshold voltages for 2nm high-performance nanosheet technology.

Figure 7 displays the four different Vt pairs and their respective performance characteristics, enabled by different integration schemes.

The optimization process requires careful consideration of NFET and PFET characteristics. The improved dual dipole integration scheme enables precise control of threshold voltage levels while maintaining device performance.

Figure 8 illustrates the mobility consistency of different Vt options in Scheme C, confirming that performance is maintained across various threshold voltage levels [1].

The successful implementation of these techniques allows for a wide range of threshold voltage options without compromising device performance or reliability. This achievement represents a significant advancement in semiconductor technology toward next-generation applications.

Figure 9 shows the full Vt range of NFET and PFET devices achieved in Scheme C of the cited paper, demonstrating the flexibility of this method.

This article introduced advanced techniques for implementing multi-Vt solutions in 2nm nanosheet technology through selective layer thinning. The combination of SLR1 and SLR2, along with improved dual dipole integration, provides a robust framework for achieving diverse threshold voltage options while maintaining device performance and reliability.

References

[1] R. Bao et al., "Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond," in 2024 International Electron Devices Meeting (IEDM), 2024.