Abstract
Semiconductor packaging plays a critical role in microelectronics by enabling integration, protection, and communication for integrated circuit chips. As advanced logic nodes and technology scaling create demanding integration requirements, advanced packaging solutions are imperative to achieve the performance gains needed for emerging applications. This paper reviews the new National Advanced Packaging Manufacturing Program (NAPMP) put forward by the United States CHIPS Research and Development Office in 2023. The NAPMP aims to establish domestic leadership in advanced packaging to enable security and resilience of semiconductor supply chains. With a $3 billion investment focused on research, piloting capabilities and workforce development, the program’s vision is for a vibrant, self-sustaining US advanced packaging industry within a decade. This paper summarizes the NAPMP strategy, key R&D thrusts and coordination with other CHIPS research programs.
Introduction
The recently passed CHIPS and Science Act offers an unprecedented opportunity for the United States to strengthen domestic capabilities across the semiconductor manufacturing value chain. The Act includes $39 billion in manufacturing incentives and research investment of $11 billion for the CHIPS Research and Development program based within the Department of Commerce and National Institute of Standards and Technology (NIST) [1]. The CHIPS program includes establishment of the National Semiconductor Technology Center (NSTC), the National Advanced Packaging Manufacturing Program (NAPMP), the CHIPS Metrology Program, and semiconductor Manufacturing USA institute(s).
This paper focuses specifically on the National Advanced Packaging Manufacturing Program first put forward in November 2023 [1]. As advanced logic scaling reaches physical limitations, advances in packaging technologies offer paths forward to achieve the integration levels, minimized form factors and demanding performance metrics required by emerging applications. However, the majority of advanced semiconductor packaging occurs offshore. The NAPMP provides strategic R&D investment to expand limited existing US packaging capabilities to enable a domestic source for advanced packaging to match front-end semiconductor manufacturing and ensure electronics supply chain security.
Figure 1 shows the interrelated key areas for NAPMP R&D investment along with the Advanced Packaging Piloting Facility for transitioning technologies to high volume manufacturing. The total $3 billion program aims to deliver leap-ahead packaging innovations to establish US leadership. This paper reviews the context, opportunities and rationale behind this major initiative along with the planned research areas and coordination with other CHIPS R&D programs.
Rationale for Advanced Packaging Investments
Semiconductor packaging protects and enables communication between integrated circuit dies. As nodes advance below 5nm, challenges arise in continuing dimensional scaling. Advanced packaging offers heterogeneous integration of multiple dies and components to provide performance gains beyond Moore’s Law scaling of CMOS logic. This is particularly crucial for improving specialized metrics like speed, power efficiency and thermal dissipation demanded by emerging workloads for AI, networking, automotive and other applications [1].
However, advanced packaging requires improvements spanning materials, assembly processes, equipment, interconnections, power delivery, thermal management and design tools. Innovation is needed across these complex interdisciplinary areas for high volume manufacturing. Establishing these capabilities domestically can enhance security for electronics supply chains given offshore reliance currently. Advanced packaging also allows customization and rapid design iterations to enable new applications. Table 1 summarizes key potential benefits compared to further CMOS scaling.
Table 1: Benefits of advanced packaging over scaling
Potential Benefits of Advanced Packaging |
Performance improvements specialized for target applications |
Reduced costs and physical footprint |
Increased chip reuse and customization |
Faster design and manufacturing ramp |
Enhanced supply chain security |
The NAPMP vision sees advanced packaging as imperative for improving electronics innovation and manufacturing self-reliance following decades of offshoring. The ambitious aim is for a vibrant domestic packaging ecosystem at commercial scale within a decade, where advanced logic chips can progress from US fabrication to US-based packing as well [1].
NAPMP Strategy and Investment Areas
The NAPMP strategy contains integrated R&D programs and an Advanced Packaging Piloting Facility (APPF) to transition successful innovations to high volume manufacturing in partnership with industry. Figure 1 illustrated the key interdependent technology and ecosystem investment areas:
Materials and Substrates: Foundation for integrating devices and wiring at high density with requirements like low warpage and high wiring complexity.
Equipment, Tools and Processes: Adapting CMOS infrastructure for advanced packaging assembly and patterning.
Power Delivery and Thermal Management: Enabling the high power densities required.
Photonics and Connectors: Supporting low loss, high bandwidth density signal transmission.
Chiplet Ecosystem: Developing interfaces and integration for modular chiplets.
Co-Design Tools: Simulation, analysis, test and security across process, materials and multi-die integration.
Additionally, workforce development in advanced packaging will be integrated throughout NAPMP activities. Table 2 outlines the expected key innovations and outcomes targeted in each area to establish leadership and commercially viable domestic capability.
Table 2: Target innovations and outcomes by NAPMP investment area
Investment Area | Innovations and Outcomes |
Materials and Substrates | Multi-level fine pitch wiring and vias, Large area, Warpage control, Embedded actives/passives |
Equipment, Tools and Processes | Die/wafer handling, Metrology, Assembly lines for advanced substrates |
Power Delivery and Thermal Management | Advanced materials and topologies for power density and heat dissipation |
Photonics and Connectors | Integrated, standards based, Configurable, Manufacturable |
Chiplet Ecosystem | Methodologies for modularization, reuse, integration |
Co-Design Tools | Simulation, analysis, test, security, manufacturability |
The APPF will offer state of the art facilities for pilot demonstration of integrated solutions from across these areas while also developing workforce skills for eventual industry adoption.
Coordination with Other CHIPS R&D Programs
While advanced packaging is crucial for heterogeneous integration to deliver necessary performance, standards and metrics are also key for adoption and commercialization. As such, the NAPMP team coordinates with other CHIPS R&D programs like the NSTC for physical integration needs and the Metrology Program to develop packaging test vehicles and measurement science. Collaboration also occurs with other government advanced assembly initiatives to share knowledge and infrastructure. Integrating findings across the CHIPS R&D efforts will strengthen outcomes in establishing domestic manufacturing leadership.
Conclusions
Electronics performance improvements through solely transistors scaling are hitting limits requiring integration breakthroughs from advanced packaging. While crucial for emerging workloads, advanced packaging development complexity has led to heavy overseas reliance creating supply vulnerabilities. The NAPMP outlined represents targeted R&D investment to pilot domestic manufacturing ecosystems for advanced logic nodes. By accelerating innovations across packaging interdisciplinary areas and transitioning results through coordinated demonstration facilities, the strategy aims for commercially viable high volume production at scale before the end of this decade. Combined with front-end fabrication incentives, the ambitious plan would complete the integrated circuit manufacturing flow within the United States to enhance innovation, job creation and national security.
References
[1] CHIPS Research and Development Office, “National Advanced Packaging Manufacturing Program Vision Paper,” U.S Department of Commerce, Nov 2023.
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