Introduction
The ever-increasing demand for higher data rates in optical communications has driven the evolution of coherent detection technology. Coherent optical systems offer superior reach, spectral efficiency, and data rates compared to traditional intensity modulation/direct detection (IM/DD) systems. However, implementing coherent receivers poses significant challenges, including ultra-wide analog bandwidth, low clock jitter, and stringent power constraints for pluggable optical modules. This article presents a state-of-the-art 200GS/s 8-bit receiver IC fabricated in a 5nm CMOS process, addressing these challenges to enable 800Gbps coherent optical communications.
Coherent Optical Communications
Coherent optical communications systems use advanced modulation formats, such as quadrature phase-shift keying (QPSK) and quadrature amplitude modulation (QAM), to encode multiple bits per symbol. This encoding, combined with dual-polarization, allows coherent systems to achieve higher spectral efficiency and data rates compared to traditional non-return-to-zero (NRZ) or pulse amplitude modulation (PAM) IM/DD systems (Figure 1).
The high data rates of coherent systems come with increased complexity in the receiver design. Coherent receivers require oversampled analog-to-digital converters (ADCs) to capture the in-phase (I) and quadrature (Q) components of the dual-polarization signal. Furthermore, the analog front-end must provide a bandwidth exceeding the symbol rate to support the required oversampling ratio and accommodate channel impairments.
As coherent technology advances, it expands into new applications beyond long-haul and metro networks, such as access, data center interconnects, and satellite communications (Figure 2). This evolution drives the need for higher data rates, wider bandwidths, and lower power consumption in coherent receiver ICs.
Receiver Architecture
The presented receiver IC employs a hierarchical sampling architecture with three layers of signal buffering and time-interleaving (Figure 3). The analog front-end, consisting of a continuous-time linear equalizer (CTLE), matching network, and active buffers, provides a bandwidth exceeding 60GHz to support the 800Gbps data rate.
The time-interleaved architecture distributes the high sampling rate across multiple parallel channels. At the first level, 16 track-and-hold amplifiers (TAHs) operate at 12.5-25GHz, capturing the input signal every 4 sample periods. The second level employs 256 sample-and-hold amplifiers (SAHs) arranged in four SAR ADC arrays, sampling at 1/16th of the TAH rate.
Clocking Scheme
The clocking scheme is crucial for maintaining synchronization across the highly parallel architecture. A central phase-locked loop (PLL) generates eight phases of the sampling clock (fs/8) at 12.5-25GHz with a 50% duty cycle. These clocks are divided by two to obtain 16 phases for the TAHs, with a fine delay-locked loop (DLL) compensating for skew. Further division by 16 generates the pulses for the 256 SAR ADCs (Figure 4).
Calibration and Correction
To maintain high linearity and accuracy across the massively parallel architecture, the receiver employs various calibration and correction techniques. Background calibration continually adjusts the amplitude, offset, and skew of individual channels, assisted by digital processing. Nonlinear digital correction and channel-to-channel alignment further enhance performance (Figure 5).
The hierarchical grouping of channels during calibration redistributes calibration ranges and maximizes yield. Child nodes are calibrated to the statistical mean of their parent nodes, relaxing the analog requirements through post-correction (Figure 6).
Analog Front-End Design
The analog front-end incorporates several innovative design techniques to achieve the required bandwidth and linearity. A negative T-coil matching network (Figures 7 and 8) increases peaking near the Nyquist frequency while trading off input return loss for improved bandwidth.
The CTLE (Figure 9) employs a PMOS topology with positive T-coil filtering, neutralization capacitors, and trimmable resistors for gain tuning. Class-AB buffers with active inductive peaking (Figure 10) provide further signal conditioning at high frequencies.
A super-source follower with gm/gm gain boosting and capacitive coupling (Figure 11) ensures fast settling and high gain in the final buffering stage before the ADCs.
SAR ADC Architecture
The receiver employs an asynchronous SAR ADC architecture (Figure 12) with continuous adaptive voltage scaling (AVS) to optimize power efficiency. The SAR logic operates based on a ring oscillator, allowing continuous tracking of the optimal supply voltage for each conversion stage.
Measurement Results
The receiver IC achieves exceptional performance, with a measured bandwidth exceeding 60GHz after accounting for channel losses (Figure 13). Low-frequency SNDR and THD measurements demonstrate the high linearity of the design, with some degradation at higher frequencies due to clock jitter and AFE nonlinearities (Figure 14).
The receiver's energy efficiency is highlighted in the Walden FOM chart (Figure 15), achieving a remarkable 20fJ/conversion-step at low frequencies and 38fJ/conversion-step at high frequencies when accounting for the complete receiver power consumption.
In comparison with prior art (Table 1), the presented receiver IC demonstrates state-of-the-art performance, with the highest reported sampling rate of 200GS/s for an optical receiver, a bandwidth exceeding 60GHz, and the lowest reported total receiver jitter of 70fs-rms, including the PLL. Additionally, it achieves the lowest reported figure of merit (FOM) of approximately 20fJ/conversion-step for a complete receiver above 100GS/s.
Conclusion
The 200GS/s 8-bit receiver IC presented in this article represents a significant advancement in coherent optical communications, enabling 800Gbps data rates while addressing the challenges of ultra-wide bandwidth, low jitter, and stringent power constraints. The hierarchical sampling architecture, innovative analog front-end design, and calibration techniques contribute to the IC's exceptional performance and energy efficiency. With its state-of-the-art specifications, this receiver paves the way for the next generation of high-speed coherent optical networks, supporting emerging applications across various domains.
Reference
[1] R. L. Nguyen, A. Mellati, A. Fernandez, et al., "A 200GS/s 8-b 20fJ/c-s Receiver with >60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET," in ISSCC 2024.
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